ETHERNET CONTROLLER
S3C4510B
MEDIA ACCESS CONTROL (MAC) REGISTERS
This section describes the control and status registers for the flow control 100-/10-Mbit/s ethernet MAC. These
include a master MAC control register, control registers for transmit and receive, control registers for the CAM, a
counter for network management, and various flow control registers (see Table 7-17).
Table 7-17. MAC Control and Status Registers
Registers
MACON
Offset
0XA000
0xA004
0xA008
0xA00C
0xA010
0xA014
0xA018
0xA01C
0xA028
0xA03C
0xA040
0xA044
0x9040
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reset Value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00006000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
MAC control
CAMCON
CAM control
MACTXCON
MACTXSTAT
MACRXCON
MACRXSTAT
STADATA
STACON
Transmit control
Transmit status
Receive control
Receive status
Station management data
Station management control and address
CAM enable
CAMEN
EMISSCNT
EPZCNT
RClr/W Missed error count
R
R
R
Pause count
ERMPZCNT
ETXSTAT
Remote pause count
Transmit control frame status
NOTE: MAC transmit/receive interrupt is generated whenever the Tx/Rx status field of Tx/Rx frame descriptor is written.
7-34
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