S3C4510B
ETHERNET CONTROLLER
MAC Transmit Control Register
To generate an interrupt after each packet, set the enable completion bit and all of the MAC error enable bits.
Using MAC transmit control register settings, you can also selectively enable interrupts for specific conditions.
Table 7-22. MACTXCON Register
Registers
Offset
R/W
Description
Transmit control
Reset Value
MACTXCON
0XA008
R/W
0x00000000
Table 7-23. MAC Transmit Control Register Description
Bit Number
Bit Name
Description
[0]
Transmit enable (TxEn)
Set this bit to enable transmission. To stop transmission
immediately, clear the transmit enable bit to "0".
[1]
Transmit halt request (TxHalt) Set this bit to halt transmission after completing any current
packet.
[2]
[3]
[4]
[5]
Suppress padding (NoPad)
Suppress CRC (NoCRC)
Fast back-off (FBack)
No defer (NoDef)
Set to not generate pad bytes for packets of less than 64 bytes.
Set to suppress addition of a CRC at the end of a packet.
Set this bit to use faster back-off times for testing.
Set to disable the defer counter. (The defer counter keeps
counting until the carrier sense (CrS) bit is turned off.)
[6]
Send Pause (SdPause)
Set this bit to send a pause command or other MAC control
packet. The send pause bit is automatically cleared when a
complete MAC control packet has been transmitted. Writing a
"0" to this register bit has no effect.
[7]
[8]
[9]
MII 10-Mb/s SQE test mode
enable (SQEn)
Set this bit to enable MII 10-Mb/s SQE test mode.
Enable underrun (EnUnder)
Set this bit to generate an interrupt if the MAC transmit FIFO is
empty during a transmission.
Enable deferral (EnDefer)
Set this bit to generate an interrupt if the MAC defers for
MAX_DEFERRAL time: "0" = 0.32768 ms at 100 Mb/s; "1" =
3.2768 ms at 10-Mb/s.
[10]
[11]
Enable no carrier (EnNCarr)
Set this bit to generate an interrupt if a carrier sense is not
detected while an entire packet is transmitted.
Enable excessive collision
(EnExColl)
Set this bit to enable an interrupt if 16 collisions occur in the
same packet.
[12]
Enable late collision
(EnLateColl)
Set this bit to generate an interrupt if a collision occurs after 512
bit times (or 64 byte times).
[13]
Enable transmit parity
(EnTxPar)
Set this bit to generate an interrupt if a parity error is detected in
the MAC transmit FIFO.
[14]
Enable completion (EnComp) Set this bit to generate an interrupt whenever the MAC
transmits or discards one packet.
[31:15]
Reserved
Not applicable.
7-37
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