S3C4510B
ETHERNET CONTROLLER
Rx Status
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[19] Over maximum size (OvMax)
Set if the received frame data size exceeds the maximum frame size.
[21] Control received (CtlRcv)
Set if the received packet is a MAC control frame.
[22] Interrupt on receive (IntRx)
Set if reception of packet caused an interrupt condition. This includes Good
received, if the Engood bit, MACRXCON [14], is set.
[23] Receive 10 Mb/s status (Rx10stat)
Set if packet was received over the 7-wire interface. Reset if packet was received
over the MII.
[24] Alignment error (AlignErr)
Frame length in bits was not a multiple of eight and the CRC was invalid.
[25] CRC Error (CRCErr)
CRC at end of packet did not match the computed value, or else the PHY
asserted Rx_er during packet reception.
[26] Overflow error (Overflow)
The MAC receive FIFO was full when it needed to store a received byte.
[27] Long error (LongErr)
Received a frame longer than 1518 bytes. Not set if the long enable bit set to one
in the receive control register.
[29] Receive parity error (RxPar)
MAC receive FIFO has detected a parity error.
[30] Good received (Good)
Successfully received a packet with no errors. If EnGood = 1, an interrupt is
generated on each packet that is received successfully.
[31] Reception halted (RxHalted)
Reception interrupted by user clearing RxEN or setting Haltlmm in the MAC
control register.
Figure 7-8. Rx Descriptor Status Bits
7-19
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