ETHERNET CONTROLLER
S3C4510B
31 30
16 15
7 6
5 4
3
2
1
0
O
Frame Data Pointer
Reserved
WA A L
Frame Length
T
C P
Tx Status
Next Frame Descriptor Pointer
[0] No-padding mode (P)
0 = Padding mode 1 = No-padding mode
[1] No-CRC mode (C)
0 = CRC mode
1 = No-CRC mode
[2] MAC transmit interrupt enable after transmission of this frame (T)
0 = Disable 1 = Enable
[3] Little-Endian mode (L)
0 = Big-endian
1 = Little-endian
[4] Frame data pointer increment/decrement (A)
0 = Decrement
1 = Increment
[6:5] Widget alignment control (WA)
(Non-aligned data must be transmitted without alignment control.)
00 = No invalid bytes
10 = Two invalid bytes
01 = One invalid byte
11 = Three invalid bytes
[31] Ownership bit (0)
0 = CPU
1 = BDMA
[30:0] Frame data pointer
The address of the frame data to be transmitted.
[15:0] Frame length
The size of the transmit frame.
[31:16] Tx status
This Tx frame status field is updated by the MAC after transmission.
[31:0] Next frame descriptor pointer
The address of the next frame descriptor.
Figure 7-7. Data Structure of Tx Frame Descriptor
7-18
SAMSUNG [ SAMSUNG ]
