ETHERNET CONTROLLER
The Bus Arbiter
S3C4510B
The bus arbiter decides which of the BDMA buffer controllers, transmit (Tx) or receive (Rx), has the highest
priority for accessing the system bus. The prioritization is dynamic. The BDMA arbiter outputs a bus request
signal (nREQ) to the system manager when
— A buffer contains more words than the Rx burst size,
— An EOF (End of Frame) was saved to the buffer, or
— A buffer contains more free space than the Tx burst size.
After it receives a bus acknowledge signal (nACK) from the system manager, the BDMA bus arbiter determines
the correct bus access priority. If nREQ_Tx and nREQ_Rx were requested simultaneously, the bus arbiter
decodes the nACK signal using the following method:
switch (Half_empty, Half_full)
{ case 2'b01: nACK_Rx ¬ nACK
case 2'b10: nACK_Tx ¬ nACK
default: //case 2'b00 or 2'b11:
if (Rx buffsize (Head - Tail) < Tx buffsize) // Rx more urgent
nACK_Rx ¬ nACK
else nACK_Tx ¬ nACK}
7-14
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