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S3C4510B 参数 Datasheet PDF下载

S3C4510B图片预览
型号: S3C4510B
PDF下载: 下载PDF文件 查看货源
内容描述: 三星S3C4510B的16位/ 32位RISC微控制器是一款高性价比,高性能的基于以太网的系统微控制器解决方案。 [Samsungs S3C4510B 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller solution for Ethernet-based systems.]
分类和应用: 微控制器以太网
文件页数/大小: 422 页 / 2160 K
品牌: SAMSUNG [ SAMSUNG ]
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ETHERNET CONTROLLER  
S3C4510B  
FLOW CONTROL BLOCK  
The flow control block provides for the following functions:  
— Recognition of MAC control frames received by the receive block  
— Transmission of MAC control frames, even if transmitter is paused  
— Timers and counters for pause operation  
— Command and status register (CSR) interface  
— Options for passing MAC control frames through to software drivers  
The receive logic in the flow control block recognizes a MAC control frame as follows:  
— The length/type field must have the special value specified for MAC control frames. The destination address  
must be recognized by the CAM. The frame length must be 64 bytes, including CRC. The CRC must be  
valid, and the frame must contain a valid pause op-code and operation.  
— If the length/type field does not have the special value specified for MAC control frames, the MAC takes no  
action, and the packet is treated as a normal packet. If the CAM does not recognize the destination address,  
the MAC rejects the packet. If the packet length is not 64 bytes, including CRC, the MAC does not perform  
the operation. The packet is then marked as a MAC control packet, and is passed forward to the software  
drivers, if pass-through is enabled.  
You can set control bits in the transmit status register to generate a Full-Duplex pause operation or other MAC  
control functions, even if the transmitter itself is paused. Two timers and two corresponding CSR registers are  
used during a pause operation. One timer/register pair is used when a received packet causes the transmitter to  
pause. The other pair is used to approximate the pause status of the other end of the link, after the transmitter  
sends a Pause command.  
The command and status register (CSR) interface provides control and status bits within the transmit and receive  
control registers and status registers. These lets you initiate the sending of a MAC control frame, enable and  
disable MAC control functions, and read the values of the flow control counters.  
Control bits are provided for processing MAC control frames entirely within the controller, or for passing MAC  
control frames on to the software drivers. This lets you enable flow control by default even on software drivers  
which are not otherwise "flow control aware".  
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