ETHERNET CONTROLLER
S3C4510B
THE MAC RECEIVE BLOCK
The MAC receive block is responsible for receiving data. It complies with the IEEE802.3 standard for carrier
sense multiple access with collision detection (CSMA/CD) protocol.
After it receives a packet, the receive block checks for a number of error conditions: CRC errors, alignment
errors, and length errors. Several of these checks can be disabled by setting bits in the appropriate control
registers. depending on the CAM status, the destination address and the receive block may reject an otherwise
acceptable packet. The MAC receive block consists of the following units:
— Receive FIFO, FIFO controller, and counters
— Receive BDI state machine
— Threshold logic and counters
— CAM block for address recognition
— Parallel CRC checker
— Receive state machine
The main components of the receive block are shown in Figure 7-4.
Rx_DB [7:0]
and parity
RxD[3:0]
Rx_clk
MAC Receive
FIFO
9
(16X10)
Parity
Check
SFD
Detect
CAM
Checker
Read
address
Write address
/WE
CRC
Checker
Rx_DV
Rx_er
Receive
State
Machine
Write FIFO
controller
and counter
Write FIFO
controller
and counter
Rx_rd
Rx_rdy
Receive
BDI state
Machine
Rx_EOF
Thershold
logic and
counter
Rx_keep
Rx_toss
Rx_load
CAM_hit#
SYS_CLK Domain
Rx_CLK Domain
Figure 7-4. MAC Receive Function Blocks
7-10
SAMSUNG [ SAMSUNG ]
