S3C4510B
ETHERNET CONTROLLER
BUFFERED DMA INTERFACE
BUFFERED DMA (BDMA) CONTROL BLOCKS
The BDMA engine controls a transmit buffer and a receive buffer. The BDMA transmit buffer holds data and
status information for packets being transmitted. The BDMA receive buffer holds data and status information for
packets being received. Each FIFO has a control block which controls data being placed in, and removed from,
the buffers.
Half_full
Half_empty
SD [31:0]
nREQ_Tx
Rx Bus
Tx_clk
Tx_wr
BDMA
Tx
Buffer
(32 x 64)
HEAD Ptr
TAIL Ptr
SD[31:0]
nACK
Tx
Control
Machine
-
Request
BUS
Arbiter
Tx_rdy
S
Y
S
T
E
M
B
D
I
Half_full
Tx_Underflow
nREQ_Rx
nREQ
Tx_DB[7:0]
Tx widget
Big/little
Word-to-Byte
Converter
B
D
M
A
SA[25:0]
Data Swapper
Big/Little
Address
Generator
B
U
S
BDMA
Rx
Buffer
(33 x 64)
HEAD Ptr
TAIL Ptr
Rx_clk
Rx_rd
Rx Bus
Request
-
I/F
Rx
Control
Machine
Target Address
for Rx
I/F
Rx_rdy
RX_over flow
Half_empty
Rx_DB[7:0]
Byte-to-Word
Converter
Source Address
for Tx
Rx_Widget
Figure 7-5. BDMA Control Blocks
7-13
SAMSUNG [ SAMSUNG ]
