S3C4510B
ETHERNET CONTROLLER
Threshold Logic and Counters
The transmit state machine uses a counter and logic to control the threshold of when transmission can begin.
before it attempts to initiate transmission, the MAC waits until eight bytes or a complete packet has been placed
in the transmit FIFO. This gives the DMA engine some latency without causing an underflow during transmission.
Back-Off and Retransmit Timers
When a collision is detected on the network, the transmitter block stops the transmission and starts a jamming
pattern to ensure that all the nodes detect the collision. After this, the transmitter waits for a minimum of 96 bit
times and then retransmits the data. After 16 attempts, the transmit state machine sets an error bit and
generates an interrupt, if enabled, to signify the failure to transmit a packet due to excessive collisions. It flushes
the FIFO, and the MAC is ready for the next packet.
Transmit Data Parity Checker
Data in the FIFO is odd-parity protected. When data is read for transmission, the transmit state machine checks
the parity. If a parity error is detected, the transmit data parity checker does the following:
— It stops transmission.
— It sets the parity error bit in the transmit status register.
— It generates an interrupt, if enabled.
Transmit State Machine
The transmit state machine is the central control logic for the transmit block. It controls the passing of signals, the
timers, and the posting of errors in the status registers.
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