SYSTEM MANAGER
S3C4510B
Table 4-5 and 4-6
Using big-endian and half-word access, Program/Data path between register and external memory.
HA=Address whose LSB is 0, 2, 4, 6, 8, A, C, E
HAU=Address whose LBS is 2, 6, A, E
HAL=Address whose LSB is 0, 4, 8, C
X=Don't care
CAS3-0/nWBE3-0=0 means active and 1 means inactive
Table 4-5. Half-Word Access Store Operation with Big-Endian
STORE (CPU Reg ® External Memory)
Ext. Memory Type
Bit Num.
Word
Half word
Byte
31
0
31
0
31 0
CPU Register Data
abcd
abcd
HA
abcd
HA
CPU Address
HAL
HAU
Bit Num.
31
0
31
0
31
0
31
0
31 0
CPU Data Bus
cdcd
cdcd
cdcd
cdcd
cdcd
Bit Num.
31
0
31
0
31
0
31
0
31 0
Internal SD Bus
cdcd
HAL
0011
cdcd
HAL
1100
cdcd
HA
cdcd
HA
cdcd
HA + 1
XXX0
External Address
CAS3-0/nWBE3-0
XX00
XXX0
Bit Num.
XDATA
31
0
31
0
15
0
7
0
7
0
cdXX
XXcd
cd
c
c
d
d
Bit Num.
Ext. Memory Data
31 16
15
0
15
0
7
0
7
0
cd
cd
cd
Timing Sequence
1st write 2nd write
Table 4-6. Half-Word Access Load Operation with Big-Endian
LOAD (CPU Reg ¬ External Memory)
Ext. Memory Type
Bit Num.
Word
Half word
Byte
15
0
15
0
15 0
CPU Register Data
ab
ab
HA
ab
HA
CPU Address
HAL
HAU
Bit Num.
31
0
31
0
31
0
31
0
31 0
CPU Data Bus
abab
cdcd
abab
aXaX
abab
Bit Num.
31
0
31
0
31
0
31
0
31 0
Internal SD Bus
abab
HAL
cdcd
HAL
abab
HA
aXaX
HA
abab
HA + 1
XXXX
External Address
CAS3-0/nWBE3-0
XXXX
XXXX
XXXX
XXXX
Bit Num.
XDATA
31
0
31
0
15
0
7
0
7
0
abcd
abcd
ab
a
a
b
b
Bit Num.
Ext. Memory Data
31
0
15
0
7
0
7
0
abcd
ab
Timing Sequence
1st read
2nd read
4-10
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