S3C4510B
SYSTEM MANAGER
Table 4-3 and Table 4-4
Using big-endian and word access, Program/Data path between register and external memory
WA=Address whose LSB is 0, 4, 8, C
X=Don't care
CAS3-0/nWBE3-0=0 means active and 1 means inactive
Table 4-3. Word Access Store Operation with Big-Endian
STORE (CPU Reg ® External Memory)
Ext. Memory Type
Word
Half Word
Byte
Bit Num.
31
0
31
0
31 0
CPU Register Data
abcd
WA
abcd
WA
abcd
WA
CPU Address
Bit Num.
31
0
31
0
31
0
31
0
31
0
31
0
31 0
CPU Data Bus
abcd
abcd
abcd
abcd
abcd
abcd
abcd
Bit Num.
31
0
31
0
31
0
31
0
31
0
31
0
31 0
Internal SD Bus
abcd
WA
abcd
WA
abcd
abcd
WA
abcd
WA + 1
XXX0
abcd
abcd
WA + 3
XXX0
External Address
CAS3-0/nWBE3-0
WA + 2
XX00
WA + 2
XXX0
0000
XX00
XXX0
Bit Num.
XDATA
31
0
15
0
15
0
7
0
7
0
7
0
7
0
abcd
ab
cd
a
a
b
b
c
c
d
d
Bit Num.
Ext. Memory Data
31
0
15
0
15
0
7
0
7
0
7
0
7
0
abcd
ab
cd
Timing Sequence
1st write 2nd write 1st write 2nd write 3rd write 4th write
Table 4-4 Word Access Load Operation with Big-Endian
LOAD (CPU Reg ¬ External Memory)
Ext. Memory Type
Word
Half Word
Byte
Bit Num.
31
0
31
0
31 0
CPU Register Data
abcd
WA
abcd
WA
abcd
WA
CPU Address
Bit Num.
31
0
31
0
31
0
31
0
31
0
31
0
31 0
CPU Data Bus
abcd
abXX
abcd
aXXX
abXX
abcX
abcd
Bit Num.
31
0
31
0
31
0
31
0
31
0
31
0
31 0
Internal SD Bus
abcd
WA
abXX
WA
abcd
aXXX
WA
abXX
WA + 1
XXX0
abcX
abcd
WA + 3
XXX0
External Address
CAS3-0/nWBE3-0
WA + 2
XX00
WA + 2
XXX0
0000
XX00
XXX0
Bit Num.
XDATA
31
0
15
0
15
0
7
0
7
0
7
0
7
0
abcd
ab
cd
a
a
b
b
c
c
d
d
Bit Num.
Ext. Memory Data
31
0
15
0
15
0
7
0
7
0
7
0
7
0
abcd
ab
cd
Timing Sequence
1st read 2nd read 1st read 2nd read 3rd read
4th read
4-9
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