S3C4510B
SYSTEM MANAGER
Table 4-9 and 4-10
Using little-endian and word access, Program/Data path between register and external memory
WA=Address whose LSB is 0,4,8,C
X=Don't care
CAS3-0/nWBE3-0=0 means active and 1 means inactive
Table 4-9. Word Access Store Operation with Little-Endian
STORE (CPU Reg ® External Memory)
Ext. Memory Type
Bit Num.
Word
Half Word
Byte
31
0
31
0
31 0
abcd
abcd
abcd
CPU Register Data
CPU Address
Bit Num.
WA
WA
WA
31
0
31
0
31
0
31
0
31
0
31
0
31 0
abcd
abcd
abcd
abcd
abcd
abcd
abcd
CPU Data Bus
Bit Num.
31
0
31
0
31
0
31
0
31
0
31
0
31 0
abcd
abcd
abcd
abcd
abcd
abcd
abcd
Internal SD Bus
External Address
Bit Num.
WA
WA
WA + 2
WA
WA + 1
WA + 2
31
0
15 0
15 0
7
7
0
0
7
7
0
0
7
7
0
0
7
7
0
0
abcd
cd
ab
d
c
c
b
b
a
XDATA
Bit Num.
31
0
15 0
15 0
abcd
cd
ab
d
a
Ext. Memory Data
Timing Sequence
1st write 2nd write 1st write 2nd write 3rd write 4th write
Table 4-10. Word Access Load Operation with Little-Endian
LOAD (CPU Reg ¬ External Memory)
Ext. Memory Type
Word
Half Word
Byte
Bit Num.
31
0
31
0
31 0
CPU Register Data
abcd
WA
abcd
WA
abcd
WA
CPU Address
Bit Num.
31
0
31
0
31
0
31
0
31
0
31
0
31 0
CPU Data Bus
abcd
XXcd
abcd
XXXd
XXcd
Xbcd
abcd
Bit Num.
31
0
31
0
31
0
31
0
31
0
31
0
31 0
Internal SD Bus
abcd
WA
XXcd
WA
abcd
XXXd
WA
XXcd
Xbcd
WA + 2
abcd
External Address
WA + 2
WA + 1
WA + 3
Bit Num.
XDATA
31
0
15 0
15 0
7
0
7
0
7
0
7
0
abcd
cd
ab
d
d
c
c
b
b
a
a
Bit Num.
Ext. Memory Data
31
0
15 0
15 0
7
0
7
0
7
0
7
0
abcd
cd
ab
Timing Sequence
1st read 2nd read 1st read 2nd read 3rd read
4th read
4-13
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