SYSTEM MANAGER
S3C4510B
EXTERNAL ADDRESS TRANSLATION METHOD DEPENDS ON THE WIDTH OF EXTERNAL MEMORY
The S3C4510B address bus is, in some respects, different than the bus used in other standard CPUs. Based on
the required data bus width of each memory bank, the internal system address bus is shifted out to an external
address bus, ADDR[21:0]. This means that memory control signals such as nRAS[3:0], nCAS[3:0], nECS[3:0],
nRCS[5:0], and nWBE[3:0] are generated by the system manager according to a pre-configured external memory
scheme (see Table 4-2). This is applied to SDRAM signals as same method.
Table 4-2. Address Bus Generation Guidelines
Data Bus Width
8-bit
External Address Pins, ADDR[21:0]
A21–A0 (internal)
Accessible Memory Size
4M bytes
16-bit
A22–A1 (internal)
4M half-words
4M words
32-bit
A23–A2 (internal)
Data Bus Width Configuration
(8-bit/16-bit/32-bit)
SA [21:0]
22-bit
8-bit
External Address Pins
ADDR [21:0]
SA [22:1]
22-bit
16-bit
32-bit
22-bit
SA [23:2]
22-bit
System Address Bus: SA [25:0]
Figure 4-3. External Address Bus Diagram
4-6
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