S3C4510B
SYSTEM MANAGER
Table 4-7 and 4-8
Using big-endian and byte access, Program/Data path between register and external memory
BA=Address whose LSB is 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
BAL=Address whose LSB is 0,2,4,6,8,A,C,E
BAU=Address whose LBS is 1,3,5,7,9,B,D,F
BA0=Address whose LSB is 0,4,8,C
BA1=Address whose LBS is 1,5,9,D
BA2=Address whose LSB is 2,6,A,E
BA3=Address whose LBS is 3,7,B,F
X=Don't care
CAS3-0/nWBE3-0=0 means active and 1 means inactive
Table 4-7. Byte Access Store Operation with Big-Endian
STORE (CPU Reg ® External Memory)
Ext. Memory Type
Bit Num.
Word
Half Word
Byte
31
0
31
0
31 0
CPU Register Data
abcd
abcd
abcd
BA
CPU Address
BA0
BA1
BA2
BA3
BAL
BAU
Bit Num.
31
0
31
0
31
0
31
0
31
0
31
0
31 0
CPU Data Bus
dddd
dddd
dddd
dddd
dddd
dddd
dddd
Bit Num.
31
0
31
0
31
0
31
0
31
0
31
0
31 0
Internal SD Bus
dddd
BA0
dddd
BA0
dddd
BA0
dddd
BA0
dddd
BAL
dddd
BAL
dddd
BA
External Address
CAS3-0/nWBE3-0
0111
1011
1101
1110
XX10
XX01
XXX0
Bit Num.
XDATA
31
0
31
0
31
0
31
0
15
0
15
0
7
0
dXXX
XdXX
XXdX
XXXd
dX
Xd
d
d
Bit Num.
Ext. Memory Data
31 24
23 16
15
8
7
0
15
0
15
0
7
0
d
d
d
d
d
d
Timing Sequence
4-11
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