SYSTEM MANAGER
S3C4510B
Table 4-11 and 4-12
Using little-endian and half-word access, Program/Data path between register and external memory
HA=Address whose LSB is 0, 2, 4, 6, 8, A, C, E
HAU=Address whose LBS is 2, 6, A, E
HAL=Address whose LSB is 0, 4, 8, C
X=Don't care
CAS3-0/nWBE3-0=0 means active and 1 means inactive
Table 4-11. Half-Word Access Store Operation with Little-Endian
STORE (CPU Reg ® External Memory)
Ext. Memory Type
Bit Num.
Word
Half word
Byte
31 d0
31
0
31 0
CPU Register Data
abcd
abcd
HA
abc
CPU Address
HAL
HAU
HA
Bit Num.
31
0
31
0
31
0
31
0
31 0
CPU Data Bus
cdcd
cdcd
cdcd
cdcd
cdcd
Bit Num.
31
0
31
0
31
0
31
0
31 0
Internal SD Bus
cdcd
HAL
1100
cdcd
HAL
0011
cdcd
HA
cdcd
HA
cdcd
HA+1
XXX0
External Address
CAS3-0/nWBE3-0
XX00
XXX0
Bit Num.
XDATA
31
0
31
0
15
0
7
0
7
0
cdcd
cdcd
cd
d
d
c
c
Bit Num.
Ext. Memory Data
15
0
31 16
15
0
7
0
7
0
cd
cd
cd
Timing Sequence
1st write 2nd write
Table 4-12. Half-Word Access Load Operation with Little-Endian
LOAD (CPU Reg ¬ External Memory)
Ext. Memory Type
Bit Num.
Word
Half word
Byte
15
0
15
0
15 0
CPU Register Data
cd
ab
HA
ba
HA
CPU Address
HAL
HAU
Bit Num.
31
0
31
0
31
0
31
0
31 0
CPU Data Bus
cdcd
abab
abab
XaXa
baba
Bit Num.
31
0
31
0
31
0
31
0
31 0
Internal SD Bus
cdcd
HAL
abab
HAL
abab
HA
XaXa
HA
baba
HA+1
XXXX
External Address
CAS3-0/nWBE3-0
XXXX
XXXX
XXXX
XXXX
Bit Num.
XDATA
31
0
31
0
15
0
7
0
7
0
abcd
abcd
ab
a
a
b
b
Bit Num.
Ext. Memory Data
31
0
15
0
7
0
7
0
abcd
ab
Timing Sequence
1st read
2nd read
4-14
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