OneNAND512Mb(KFG1216U2B-xIB6)
FLASH MEMORY
7.0 TECHNICAL AND APPLICATION NOTES
From time-to-time supplemental technical information and application notes pertaining to the design and operation of the device in a
system are included in this section. Contact your Samsung Representative to determine if additional notes are available.
7.1
Methods of Determining Interrupt Status
There are two methods of determining Interrupt Status on the OneNAND. Using the INT pin or monitoring the Interrupt Status Regis-
ter Bit.
The OneNAND INT pin is an output pin function used to notify the Host when a command has been completed. This provides a hard-
ware method of signaling the completion of a program, erase, or load operation.
In its normal state, the INT pin is high if the INT polarity bit is default. In case of normal INT mode, before a command is written to the
command register, the INT bit must be written to '0' so the INT pin transitions to a low state indicating start of the operation. In case of
’INT auto mode’, INT bit is written to ’0’ automatically right after command issued. Upon completion of the command operation by the
OneNAND’s internal controller, INT returns to a high state.
INT pin is a DQ-type output allowing two INT outputs to be Or-tied together. Refer to section 2.8 for additional information about INT.
At previous 512Mb OneNAND, INT pin operates as an open-drain type. But at current 512Mb B-die OneNAND, INT pin operates as a
DQ-type which has faster responsiveness than open drain type. Although DQ-type INT pin is connected to pull-up resistor, DQ-type
INT pin will not be affected by the resistor.
INT can be implemented by tying INT to a host GPIO or by continuous polling of the Interrupt status register.
INT Type (Mono)
DQ type
General Operation
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