OneNAND512Mb(KFG1216U2B-xIB6)
FLASH MEMORY
7.1.2 Polling the Interrupt Register Status Bit
An alternate method of determining the end of an operation is to continuously monitor the Interrupt Status Register Bit instead of
using the INT pin.
When using interrupt register instead of INT pin, INT may be unconnected.
Command
INT
This can be configured in either a synchronous mode or an asynchronous mode.
Synchronous Mode Using Interrupt Status Register Bit Polling
When operating synchronously, CE and AVD of the OneNAND are tied to CE of the Host, CLK, OE, and DQ pins on the host and
OneNAND are tied together. RDY could be connected as one of following guides.
Host
CE
OneNAND
Host
CE
OneNAND
CE
CE
AVD
CLK
RDY
OE
AVD
CLK
RDY
OE
CLK
RDY(WAIT)
OE
CLK
OE
DQ
DQ
DQ
DQ
Handshaking Mode
Asynchronous Mode Using Interrupt Status Register Bit Polling
Non-Handshaking Mode
When configured to operate in an asynchronous mode, CE and AVD of the OneNAND are tied to CE of the Host. CLK is tied to the
Host Vss (Ground). RDY is NOT connected. OE and DQ of the OneNAND and Host are tied together.
Host
CE
OneNAND
CE
AVD
CLK
RDY
OE
Vss
N.C
OE
DQ
DQ
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