OneNAND512Mb(KFG1216U2B-xIB6)
FLASH MEMORY
7.1.1 The INT Pin to a Host General Purpose I/O
INT can be tied to a Host GPIO to detect the rising edge of INT, signaling the end of a command operation.
COMMAND
INT
This can be configured to operate either synchronously or asynchronously as shown in the diagrams below.
Synchronous Mode Using the INT Pin
When operating synchronously, INT is tied directly to a Host GPIO. RDY could be conneceted as one of following guides.
Host
CE
OneNAND
Host
CE
OneNAND
CE
CE
AVD
CLK
RDY
OE
AVD
CLK
RDY
OE
CLK
RDY(WAIT)
OE
CLK
OE
GPIO
INT
GPIO
INT
Handshaking Mode
Asynchronous Mode Using the INT Pin
Non-Handshaking Mode
When configured to operate in an asynchronous mode, CE and AVD of the OneNAND are tied to CE of the Host. CLK is tied to the
Host Vss (Ground). RDY is NOT connected. OE of the OneNAND and Host are tied together and INT is tied to a GPIO.
Host
CE
OneNAND
CE
AVD
CLK
RDY
OE
Vss
OE
GPIO
INT
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