K9W4G08U1M
K9K2G08Q0M
K9K2G08U0M
K9W4G16U1M
K9K2G16Q0M
K9K2G16U0M
FLASH MEMORY
VALID BLOCK
Parameter
Symbol
NVB
Min
2008
4016*
Max
2048
4096*
Unit
K9K2GXXX0M
K9W4GXXU1M
Valid Block Number
Valid Block Number
Blocks
Blocks
NVB
NOTE :
1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-
sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro-
gram factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase
cycles.
* : Each K9K2GXXX0M chip in the K9W4GXXU1M has Maximum 40 invalid blocks.
AC TEST CONDITION
(K9XXGXXXXM-XCB0 :TA=0 to 70°C, K9XXGXXXXM-XIB0:TA=-40 to 85°C
K9K2GXXQ0M : Vcc=1.70V~1.95V , K9XXGXXUXM : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9K2GXXQ0M
0V to Vcc
5ns
K9XXGXXUXM
0.4V to 2.4V
5ns
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Vcc/2
1.5V
K9K2GXXQ0M:Output Load (Vcc:1.8V +/-10%)
K9XXGXXUXM:Output Load (Vcc:3.0V +/-10%)
1 TTL GATE and CL=30pF
-
1 TTL GATE and CL=50pF
1 TTL GATE and CL=100pF
K9XXGXXUXM:Output Load (Vcc:3.3V +/-10%)
CAPACITANCE(TA=25°C, VCC=1.8V/3.3V, f=1.0MHz)
Max
K9W4GXXU1M
40
40
Item
Symbol
Test Condition
Unit
K9K2GXXX0M
Input/Output Capacitance
Input Capacitance
CI/O
CIN
VIL=0V
VIN=0V
20
20
pF
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
H
L
ALE
L
CE
L
WE
RE
H
WP
PRE
Mode
Command Input
X
X
Read Mode
H
L
H
X
X
Address Input(5clock)
Command Input
H
L
L
L
H
H
X
Write Mode
H
L
H
H
X
Address Input(5clock)
L
L
L
H
H
X
Data Input
L
L
L
H
X
X
X
X
X
X
X
Data Output
X
X
X
X
X
X
H
H
X
X
X
X
X
X
During Read(Busy)
During Program(Busy)
During Erase(Busy)
Write Protect
X
X
H
X
X
X
X
H
L
X(1)
X
X
X
(2)
(2)
X
Stand-by
0V/VCC
0V/VCC
NOTE : 1. X can be VIL or VIH.
2. WP and PRE should be biased to CMOS high or CMOS low for standby.
13
SAMSUNG [ SAMSUNG ]
