K9W4G08U1M
K9K2G08Q0M
K9K2G08U0M
K9W4G16U1M
K9K2G16Q0M
K9K2G16U0M
FLASH MEMORY
Figure 1-2. K9K2G16X0M (X16) Functional Block Diagram
VCC
VSS
2048M + 64M Bit
NAND Flash
ARRAY
X-Buffers
Latches
& Decoders
A11 - A27
A0 - A10
(1024 + 32)Word x 131072
Data Register & S/A
Y-Buffers
Latches
& Decoders
Cache Register
Y-Gating
Command
Command
Register
VCC
VSS
I/O Buffers & Latches
Global Buffers
CE
RE
WE
Control Logic
& High Voltage
Generator
I/0 0
Output
Driver
I/0 15
CLE ALE PRE
WP
Figure 2-2. K9K2G16X0M (X16) Array Organization
1 Block = 64 Pages
(64K + 2k) Word
1 Page = (1K + 32)Words
1 Block = (1K + 32)Word x 64 Pages
= (64K + 2K) Words
1 Device = (1K+32)Word x 64Pages x 2048 Blocks
= 2112 Mbits
128K Pages
(=2,048 Blocks)
16 bit
1K Words
32 Words
32 Words
I/O 0 ~ I/O 15
Page Register
1K Words
I/O 0
A0
I/O 1
I/O 2
A2
I/O 3
I/O 4
A4
I/O 5
A5
I/O 6
A6
I/O 7
A7
I/O8 ~ 15
Column Address
Column Address
Row Address
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
A1
A9
A3
*L
*L
*L
*L
*L
*L
A8
A10
A13
A21
*L
*L
*L
*L
*L
A11
A19
A27
A12
A20
*L
A14
A22
*L
A15
A23
*L
A16
A24
*L
A17
A25
*L
A18
A26
*L
Row Address
Row Address
NOTE : Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
10
SAMSUNG [ SAMSUNG ]
