K9W4G08U1M
K9K2G08Q0M
K9K2G08U0M
K9W4G16U1M
K9K2G16Q0M
K9K2G16U0M
FLASH MEMORY
Figure 1-1. K9K2G08X0M (X8) Functional Block Diagram
VCC
VSS
2048M + 64M Bit
NAND Flash
ARRAY
X-Buffers
Latches
& Decoders
A12 - A28
A0 - A11
(2048 + 64)Byte x 131072
Data Register & S/A
Y-Buffers
Latches
& Decoders
Cache Register
Y-Gating
Command
Command
Register
VCC
VSS
I/O Buffers & Latches
Global Buffers
CE
RE
WE
Control Logic
& High Voltage
Generator
I/0 0
Output
Driver
I/0 7
CLE ALE PRE
WP
Figure 2-1. K9K2G08X0M (X8) Array Organization
1 Block = 64 Pages
(128K + 4k) Byte
1 Page = (2K + 64)Bytes
1 Block = (2K + 64)B x 64 Pages
= (128K + 4K) Bytes
1 Device = (2K+64)B x 64Pages x 2048 Blocks
= 2112 Mbits
128K Pages
(=2,048 Blocks)
8 bit
2K Bytes
64 Bytes
64 Bytes
I/O 0 ~ I/O 7
Page Register
2K Bytes
I/O 0
A0
I/O 1
A1
I/O 2
I/O 3
A3
I/O 4
A4
I/O 5
A5
I/O 6
A6
I/O 7
A7
Column Address
Column Address
Row Address
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
A2
A10
A14
A22
*L
A8
A9
A11
A15
A23
*L
*L
*L
*L
*L
A12
A20
A28
A13
A21
*L
A16
A24
*L
A17
A25
*L
A18
A26
*L
A19
A27
*L
Row Address
Row Address
NOTE : Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
9
SAMSUNG [ SAMSUNG ]
