K9K1208Q0C
K9K1208D0C
K9K1208U0C
K9K1216Q0C
K9K1216D0C
K9K1216U0C
FLASH MEMORY
Figure 1-2. K9K1216X0C (X16) FUNCTIONAL BLOCK DIAGRAM
VCC
VSS
X-Buffers
A9 - A25
Latches
512M + 16M Bit
NAND Flash
ARRAY
& Decoders
Y-Buffers
Latches
A0 - A7
& Decoders
(256 + 8)Word x 131072
Page Register & S/A
Y-Gating
Command
Command
Register
VCC/VCCQ
VSS
I/O Buffers & Latches
Global Buffers
CE
RE
WE
Control Logic
& High Voltage
Generator
I/0 0
Output
Driver
I/0 15
CLE ALE
WP
Figure 2-2. K9K1216X0C (X16) ARRAY ORGANIZATION
1 Block =32 Pages
= (8K + 256) Word
1 Page = 264 Word
1 Block = 264 Word x 32 Pages
= (8K + 256) Word
1 Device = 264Words x 32Pages x 4096 Blocks
= 528 Mbits
128K Pages
(=4,096 Blocks)
Page Register
(=256 Words)
16 bit
256Word
8 Word
8 Word
I/O 0 ~ I/O 15
Page Register
256 Word
I/O 0
A0
I/O 1
A1
I/O 2
A2
I/O 3
I/O 4
A4
I/O 5
A5
I/O 6
A6
I/O 7
A7
I/O8 to 15
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
A3
A12
A20
L*
L*
L*
L*
L*
Column Address
Row Address
(Page Address)
A9
A10
A18
L*
A11
A19
L*
A13
A21
L*
A14
A22
L*
A15
A23
L*
A16
A24
L*
A17
A25
NOTE : Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
7
SAMSUNG [ SAMSUNG ]
