欢迎访问ic37.com |
会员登录 免费注册
发布采购

K9F5608U0 参数 Datasheet PDF下载

K9F5608U0图片预览
型号: K9F5608U0
PDF下载: 下载PDF文件 查看货源
内容描述: 32M ×8位NAND闪存 [32M x 8 Bit NAND Flash Memory]
分类和应用: 闪存
文件页数/大小: 29 页 / 608 K
品牌: SAMSUNG [ SAMSUNG ]
 浏览型号K9F5608U0的Datasheet PDF文件第3页浏览型号K9F5608U0的Datasheet PDF文件第4页浏览型号K9F5608U0的Datasheet PDF文件第5页浏览型号K9F5608U0的Datasheet PDF文件第6页浏览型号K9F5608U0的Datasheet PDF文件第8页浏览型号K9F5608U0的Datasheet PDF文件第9页浏览型号K9F5608U0的Datasheet PDF文件第10页浏览型号K9F5608U0的Datasheet PDF文件第11页  
K9F5608U0A-YCB0,K9F5608U0A-YIB0  
FLASH MEMORY  
VALID BLOCK  
Parameter  
Symbol  
Min  
Typ.  
Max  
Unit  
Valid Block Number  
NVB  
2013  
-
2048  
Blocks  
NOTE :  
1. The K9F5608U0A may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks  
is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or  
program factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.  
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.  
AC TEST CONDITION  
(K9F5608U0A-YCB0 :TA=0 to 70°C, K9F5608U0A-YIB0:TA=-40 to 85°C, VCC=2.7V~3.6V unless otherwise)  
Parameter  
Value  
0.4V to 2.4V  
Input Pulse Levels  
Input Rise and Fall Times  
Input and Output Timing Levels  
Output Load (3.0V +/-10%)  
Output Load (3.3V +/-10%)  
5ns  
1.5V  
1 TTL GATE and CL=50pF  
1 TTL GATE and CL=100pF  
CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)  
Item  
Symbol  
Test Condition  
Min  
Max  
10  
Unit  
pF  
Input/Output Capacitance  
Input Capacitance  
CI/O  
VIL=0V  
-
-
CIN  
VIN=0V  
10  
pF  
NOTE : Capacitance is periodically sampled and not 100% tested.  
MODE SELECTION  
CLE  
H
L
ALE  
L
CE  
L
WE  
RE  
H
GND  
X
WP  
Mode  
X
Command Input  
Read Mode  
H
L
H
X
X
Address Input(3clock)  
Command Input  
H
L
L
L
H
X
H
Write Mode  
Data Input  
H
L
H
X
H
Address Input(3clock)  
L/H(3)  
L/H(3)  
L/H(3)  
L/H(3)  
X
L
L
L
H
H
L
L
L
H
H
X
X
X
X
X
Sequential Read & Data Output  
During Read(Busy)  
During Program(Busy)  
During Erase(Busy)  
Write Protect  
L
L
L
H
X
X
X
X
X
X
X
X
X
X
H
H
X
X
H
L
X(1)  
X
X
X
(2)  
(2)  
X
Stand-by  
0V/VCC  
0V/VCC  
NOTE : 1. X can be VIL or VIH.  
2. WP should be biased to CMOS high or CMOS low for standby.  
3. When GND input is high, spare area is deselected.  
Program/Erase Characteristics  
Parameter  
Symbol  
Min  
Typ  
Max  
500  
2
Unit  
Program Time  
tPROG  
-
-
-
-
200  
ms  
Main Array  
-
-
cycles  
cycles  
ms  
Number of Partial Program Cycles  
in the Same Page  
Nop  
Spare Array  
3
Block Erase Time  
tBERS  
2
3
7
 复制成功!