Preliminary
K5A3x80YT(B)C
MCP MEMORY
SRAM TIMING DIAGRAMS
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tCW(2)
tWR(4)
CS1
CS2
S
S
tAW
tCW(2)
tBW
UB, LB
WE
tWP(1)
tAS(3)
tDW
tDH
High-Z
High-Z
Data in
Data out
Data Valid
tWHZ
tOW
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1S Controlled)
tWC
Address
tAS(3)
tCW(2)
tAW
tWR(4)
CS1
CS2
S
S
tBW
UB, LB
WE
tWP(1)
tDW
tDH
Data Valid
Data in
Data out
High-Z
High-Z
Revision 0.0
November 2002
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