256M GDDR3 SDRAM
K4J55323QG
WRITE to PRECHARGE
T0
T1
T2
T3
T3n
T4
T4n
T5
T8
T9
T10
T11
/CK
CK
COMMAND
ADDRESS
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
tWR
PRE
NOP
tRP
NOP
Bank
Col b
Bank
(a or all)
tDQSS
tDQSS (NOM)
WDQS
DI
b
DQ
DM
tDQSS
tDQSS (MIN)
WDQS
DI
DQ
DM
b
tDQSS
tDQSS (MAX)
WDQS
DI
b
DQ
DM
DON’T CARE
TRANSITIONING DATA
NOTE :
1. DI b = data-in for column b.
2. Three subsequent elements of data-in the programmed order following DI b.
3. A burst of 4 is shown.
4. A8 is LOW with the WRITE command (auto precharge is disabled).
5. WRITE latency is set to 3
38 of 53
Rev. 1.1 November 2005
SAMSUNG [ SAMSUNG ]
