Rev. 1.01
K4B2G0446D
K4B2G0846D
datasheet
DDR3L SDRAM
14. Timing Parameters by Speed Grade
[ Table 49 ] Timing Parameters by Speed Bin
Speed
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units
NOTE
Parameter
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Clock Timing
tCK(DLL_OF
F)
Minimum Clock Cycle Time (DLL off mode)
8
-
8
-
8
-
8
-
ns
6
Average Clock Period
Clock Period
tCK(avg)
tCK(abs)
See Speed Bins Table
ps
ps
tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max +
tJIT(per)min
tJIT(per)max
tJIT(per)min
tJIT(per)max
tJIT(per)min
tJIT(per)max
tJIT(per)min
tJIT(per)max
Average high pulse width
tCH(avg)
tCL(avg)
0.47
0.53
0.47
0.53
0.47
0.53
0.47
0.53
tCK(avg)
Average low pulse width
0.47
0.53
0.47
0.53
0.47
0.53
0.47
0.53
tCK(avg)
ps
Clock Period Jitter
tJIT(per)
-100
100
-90
90
-80
80
-70
70
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
tJIT(per, lck)
tJIT(cc)
-90
90
-80
80
-70
70
-60
60
ps
200
180
180
160
160
140
140
120
ps
Cycle to Cycle Period Jitter during DLL locking period
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
tJIT(cc, lck)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6per)
tERR(7per)
tERR(8per)
tERR(9per)
tERR(10per)
tERR(11per)
tERR(12per)
ps
- 147
- 175
- 194
- 209
- 222
- 232
- 241
- 249
- 257
- 263
- 269
147
175
194
209
222
232
241
249
257
263
269
- 132
- 157
- 175
- 188
- 200
- 209
- 217
- 224
- 231
- 237
- 242
132
157
175
188
200
209
217
224
231
237
242
- 118
- 140
- 155
- 168
- 177
- 186
- 193
- 200
- 205
- 210
- 215
118
140
155
168
177
186
193
200
205
210
215
-103
-122
-136
-147
-155
-163
-169
-175
-180
-184
-188
103
122
136
147
155
163
169
175
180
184
188
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min
tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max
Cumulative error across n = 13, 14 ... 49, 50 cycles
tERR(nper)
ps
24
Absolute clock HIGH pulse width
Absolute clock Low pulse width
Data Timing
tCH(abs)
tCL(abs)
0.43
0.43
-
-
0.43
0.43
-
-
0.43
0.43
-
-
0.43
0.43
-
-
tCK(avg)
tCK(avg)
25
26
DQS,DQS to DQ skew, per group, per access
DQ output hold time from DQS, DQS
DQ low-impedance time from CK, CK
DQ high-impedance time from CK, CK
tDQSQ
tQH
-
200
-
-
150
-
-
125
-
-
100
-
ps
tCK(avg)
ps
13
0.38
-800
-
0.38
-600
-
0.38
-500
-
0.38
-450
-
13, g
tLZ(DQ)
tHZ(DQ)
400
400
300
300
250
250
225
225
13,14, f
13,14, f
ps
1.35V
tDS(base)
AC160
90
75
40
25
-
-
-
-
-
-
-
-
-
-
-
-
-
ps
ps
ps
ps
ps
d, 17
d, 17
d, 17
d, 17
-
-
-
-
-
-
-
-
-
-
Data setup time to DQS, DQS referenced to
IH
V
(AC)V (AC) levels
IL
1.5V
tDS(base)
AC175
-
1.35V
tDH(base)
DC90
160
150
140
110
100
90
75
1.5V
65
1.35V
45
1.5V
55
45
25
Data hold time from DQS, DQS referenced to
(AC)V (AC) levels
V
IH
IL
tDH(base)
DC100
tDS(base)
AC135
Data setup time to DQS, DQS referenced to
(AC)V (AC) levels
V
IH
IL
tDS(base)
AC150
125
600
75
30
-
10
-
ps
ps
-
-
-
-
DQ and DM Input pulse width for each input
tDIPW
490
400
360
28
-
-
- 48 -
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