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AL2007LA 参数 Datasheet PDF下载

AL2007LA图片预览
型号: AL2007LA
PDF下载: 下载PDF文件 查看货源
内容描述: 锁相环(PLL)频率上的单片结构构成CMOS中合成 [Phase-Locked Loop (PLL) frequency synthesizer constructed in CMOS on single monolithic structure]
分类和应用:
文件页数/大小: 16 页 / 242 K
品牌: SAMSUNG [ SAMSUNG ]
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AL2007LA  
0.35µm 20MHZ-170MHZ FSPLL  
FEEDBACK REQUEST  
Thank you for having an interest in our products. Please fill out this form, especially the items which you want to  
request.  
Parameter  
Customer  
SEC  
Unit  
Process  
Supply voltage (VDD)  
Input frequency (FIN)  
Output frequency (FOUT)  
Cycle to cycle jitter (TJCC)  
100M ~ 200M  
200M ~ 300M  
300M ~ 400M  
400M ~ 500M  
100M ~ 200M  
200M ~ 300M  
300M ~ 400M  
400M ~ 500M  
Period jitter (TJP)  
Output duty ratio (TOD)  
Lock up time (TLT)  
Dynamic current  
Stand by current  
Filter capacitor  
— How many PLLs are embedded in your system ?  
— Do you need synchronization between input clock and output clock ?  
— Do you need another spec of jitter ?  
Parameter  
Long-term jitter (TJLT)  
Tracking Jitter (TJT)  
Customer  
Unit  
psec (pk-pk)  
psec (pk-pk)  
If you have another special request, please describe below.  
14  
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