0.35µm 20MHZ-170MHZ FSPLL
AL2007LA
DESIGN CONSIDERATIONS
The following design consideratios apply:
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Phase tolerance and jitter are independent of the PLL frequency.
Jitter is affected by the noise frequency in the power(VDD/VSS,VDDA/VSSA). It increases when the noise
level increases.
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A CMOS-level input reference clock is recommend for signal compatibility with the PLL circuit. Other levels
such as TTL may degrade the tolerances.
The use of two, or more PLLs requires special design considerations. Please consult your application engineer
for more information.
The following apply to the noise level, which can be minimized by using good analog power and ground
isolation techniques in the system:
- Use wide PCB traces for POWER(VDD/VSS, VDDA/VSSA) connections to the PLL core.
Seperate the traces from the chip's VDD/VSS,VDDA/VSSA supplies.
- Use proper VDD/VSS,VDDA/VSSA de-coupling.
- Use good power and ground sources on the board.
- Use Power VBB for minimize substrate noise
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The PLL core should be placed as close as possible to the dedicated loop filter and analog Power and ground
pins.
It is inadvisable to locate noise-generating signals, such as data buses and high-current outputs, near the PLL
I/O cells.
Other related I/O signals should be placed near the PLL I/O but do not have any pre-defined placement
restriction
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