AL2007LA
0.35µm 20MHZ-170MHZ FSPLL
PACKAGE PIN DESCRIPTION
Name
VDDD
VSSD
Pin No
35,36
33,34
18
I/O Type
DP
Pin Description
Digital power supply
Digital ground
DG
DI
PWRDN
FSPLL clock power down
-PWRDN is High, PLL do not operating under this
condition.
- If isn't used this pin, tied to VSS.
P[0]~P[5]
VDDA
VSSA
VBBA
FIN
1,2,45~48
13,14
11,12
19,20
15
DI
AP
AG
AB/DB
AI
DO
Pre-Divider Input(LSB)
Analog power supply
Analog ground
Analog / Digtal Sub Bias Power
Crystal input or external FREF input
20MHZ~170MHz clock output
Pump out is connected to the FILTER.
A 820pF Capcitor is connected between the pin and
analog pin
FOUT
FILTER
22
17
AO
TSEL0
TSEL1
30
29
DI
DI
FOUT divide control pins.
-End users used not this pins, tied to VDD or VSS
FOUT divide control pins.
-End users used not this pins, tied to VDD or VSS
S[0]~S[1]
M[0]~M[7]
VDDO
31,32
37~44
28
DI
DI
PP
PG
Post scaler input
8bit main divider input
I/O PAD Power
VSSO
27
I/O PAD Ground
NOTE: I/O TYPE PP and PG denote PAD power and PAD ground respectively.
12
SAMSUNG [ SAMSUNG ]
