0.35µm 20MHZ-170MHZ FSPLL
AL2007LA
PACKAGE CONFIGURATION
Dummy Test Block Control pins
2bit Post Scaler
L
L
L
L
3.3V I/O Power
C
3.3V Digital PAD Power
C
H
H
H
H
36
35
34
33
32
31
30
29
28
27
26
25
S
S
V
V
V
S
V
T
S
E
L
0
T
V
D
D
O
V
S
N
C
N
C
0
1
S
E
L
1
D
D
D
D
D
D
S
S
D
8bit Main Divider
S
S
24
23
22
21
20
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
37
38
39
40
41
42
43
44
45
46
47
48
O
M0
M1
M2
M3
M4
M5
M6
M7
P0
D
NC
FOUT
NC
H
H
H
H
H
H
H
H
H
NC
al2007la
VBBA
VBBA 19
18
H
L
C
PWRDN
820pF
103
10uF
17
16
15
14
13
FILTER
NC
External Clock Source
P1
FIN
P2
VDDA
C
V
S
V
VDDA
P3
S
S
A
P
4
P
5
N
C
3
N
C
4
N
C
5
N
C
N
N
C
8
N
C
9
N
C
10
S
3.3V Analog Power
6bit Pre Divider Input
C
7
A
11
1
2
6
12
H
L
H
L
NOTES:
1. TSEL0,TSEL1 pins are internal dummy block test pins.
2. NC is Noconnection pin
11
SAMSUNG [ SAMSUNG ]
