0.35µm 20MHZ-170MHZ FSPLL
µ
AL2007LA
CORE LAYOUT GUIDE
— The digital power(VDD,VSS) and the analog power(VDA,VSSA) must be dedicated to PLL only and seperated.
If the dedicated VDD and VSS is not allowed that of the least power consuming block is shared with the PLL.
— The PIA pad is used as a FILTER pad that contains only ESD production diodes without any resistors and
buffers.
— The FOUT and FILTER pins must be placed far from the internal signals in order to avoid overlapping signal
lines.
— The blocks having a large digital switching current must be located away from the PLL core.
— The PLL core must be shielded by guardring.
— For the FOUT pad, you can use a custom drive buffer or POT12 buffer considering the drive current.
WITHOUT XTAL-DRIVER USERS GUIDE
— There are two crystal driver cell (XTAL-OSC and PSOSCM2) options for the AL2007LA PLL core.
1. If the crystal component not used , an external clock source is applied to the FIN
* Please contact an SEC application engineer when using a crystal.
2. If the crystal component not used , an external clock I/O Buffer offered from Samsung's STD90 library is
recommanded for use
– When implementing an embedded PLL block, the following pins must be bypassed externally for testing
the PLL locking function:
* Without Xtal-driver : FIN,FILTER,FOUT,VDDA,VSSA,VDD and VSS.
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SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
