AL2007LA
0.35µm 20MHZ-170MHZ FSPLL
µ
CORE EVALUATION GUIDE
For the embedded PLL, we must consider the test circuits for the embedded PLL core inmultiple applications.
Hence the following requirements should be satisfied.
— The FILTER and FOUT pins must be bypassed for external test.
— For PLL test (Below 2 examples), it is needed to control the dividers - M[7:0],P[5:0] and S[1:0] -that generate
multiple clocks.
Example #1. Registers can be used for easy control of divider values.
Example #2. N sample bits of 16-bit divider pins can be bypassed for test using MUX.
3.3V
Power
Digital
3.3V Analog Power
External Clock Source
FIN
GND
GND
VDD VSS
VDDA VSSA VBBA
FOUT
PWRDN
M[7:0]
al2007la
FILTER
#1.16bit Register Block
P[5:0]
820pF
S[1:0]
VSSA
Select Pin
NOTES
Test Pins of N Sample bits
Internal Divider Signal Line
#2
M
U
X
: 10uF ELECTROLYTIC CAPACITOR
UNLESS OTHERWISE SPECIFIED
: 103 CERAMIC CAPACITOR
UNLESS OTHERWISE SPECIFIED
8
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
