AD7656-1/AD7657-1/AD7658-1
Data Sheet
The first bit of the conversion result is valid on the first SCLK
16 clock pulses must be provided to the AD7656-1/AD7657-1/
AD7658-1. Figure 34 shows how a 16-SCLK read is used to
access the conversion results.
CS
falling edge after the
falling edge. The subsequent 15 data
bits are clocked out on the rising edge of the SCLK signal. Data
is valid on the SCLK falling edge. To access each conversion result,
CONVST A,
CONVST B,
CONVST C
tCONV
tACQ
BUSY
CS
16
32
SCLK
tQUIET
DOUT A
V1
V3
V5
V2
V4
V6
DOUT B
DOUT C
Figure 32. Serial Interface with Three DOUT Lines
CS
48
SCLK
DOUT A
DOUT B
V5
V6
V1
V3
V2
V4
Figure 33. Serial Interface with Two DOUT Lines
t1
CONVST A,
CONVST B,
CONVST C
t10
tACQ
tCONV
t2
BUSY
ACQUISITION
CONVERSION
ACQUISITION
CS
tQUIET
t19
t18
SCLK
t16
t17
t20
DOUT A,
DOUT B,
DOUT C
t21
DB15
DB14
DB13
DB1
DB0
Figure 34. Serial Read Operation
Rev. D | Page 26 of 32
ROCHESTER [ Rochester Electronics ]
