R8C/13 Group
13. Serial Interface
13. Serial Interface
Serial interface is configured with two channels: UART0 to UART1. UART0 and UART1 each have an
exclusive timer to generate a transfer clock, so they operate independently of each other.
Figure 13.1 shows a block diagram of UARTi (i=0, 1). Figure 13.2 shows a block diagram of the UARTi
transmit/receive.
UART0 has two modes: clock synchronous serial I/O mode, and clock asynchronous serial I/O mode (UART
mode).
UART1 has only one mode, clock asynchronous serial I/O mode (UART mode).
Figures 13.3 to 13.5 show the UARTi-related registers.
Main clock or on-chip oscillator clock
f
1SIO
8SIO
32SIO
1/8
f
1/4
f
(UART0)
RxD0
TxD0
UART reception
Receive
clock
1/16
1/16
Reception
control circuit
Clock synchronous
type
CLK1 to CLK0=002
Transmit/
receive
unit
f1SIO
f8SIO
f32SIO
Internal
External
=012
=102
U0BRG register
1/(n0+1)
UART transmission
Transmit
clock
Transmission control
circuit
Clock synchronous
type
Clock synchronous type
(when internal clock is selected)
1/2
CKDIR=0
Clock synchronous type
(when external clock is selected)
CKDIR=1
Clock synchronous type
(when internal clock is selected)
CLK
polarity
reversing
circuit
CLK0
(UART1)
TXD1EN
RxD1
TxD10
TxD11
UART reception
Reception
control circuit
1/16
TXD1SEL=1
Reception
control circuit
Transmit/
receive
unit
CLK1 to CLK0=002
U1BRG
register
f1SIO
f8SIO
f32SIO
=012
=102
Internal
TXD1SEL=0
UART transmission
Transmission
control circuit
1/(n1+1)
1/16
Transmission
control circuit
To P00
Figure 13.1 UARTi (i=0, 1) Block Diagram
Rev.1.20 Jan 27, 2006 page 109 of 205
REJ09B0111-0120
RENESAS [ RENESAS TECHNOLOGY CORP ]
