3858 Group
WATCHDOG TIMER
Bit 6 of Watchdog Timer Control Register
When bit 6 of the watchdog timer control register is “0”, the MCU
enters the stop mode by execution of STP instruction. Just after
releasing the stop mode, the watchdog timer restarts counting
(Note). When executing the WIT instruction, the watchdog timer
does not stop.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and an 8-bit watchdog timer H.
Initial Value of Watchdog Timer
When bit 6 is “1”, execution of STP instruction causes an internal
reset. When this bit is set to “1” once, it cannot be rewritten to “0”
by program. Bit 6 is “0” at reset.
At reset or writing to the watchdog timer control register (address
003916), each of watchdog timer H and L is set to “FF16”. Any in-
struction which generates a write signal such as the instructions of
STA, LDM, CLB and others can be used to write. The data of bits
6 and 7 are only valid when writing to the watchdog timer control
register. Each of watchdog timer is set to “FF16” regardless of the
written data of bits 0 to 5.
The necessary time after writing to the watchdog timer control reg-
ister to an underflow of the watchdog timer H is shown as follows.
When bit 7 of the watchdog timer control register is “0”:
32 s at XCIN = 32.768 kHz frequency and
65.536 ms at XIN = 16 MHz frequency.
Operation of Watchdog Timer
When bit 7 of the watchdog timer control register is “1”:
125 ms at XCIN = 32.768 kHz frequency and
The watchdog timer stops at reset and starts to count down by
writing to the watchdog timer control register. An internal reset oc-
curs at an underflow of the watchdog timer H. The reset is
released after waiting for a reset release time and the program is
processed from the reset vector address. Accordingly, program-
ming is usually performed so that writing to the watchdog timer
control register may be started before an underflow of the watch-
dog timer H. If writing to the watchdog timer control register is not
performed once, the watchdog timer does not function.
256 µs at XIN = 16 MHz frequency.
Note: The watchdog timer continues to count for waiting for a stop mode re-
lease time. Do not generate an underflow of the watchdog timer H
during that time.
“FF16” is set when
watchdog timer
Data bus
“FF16” is set when
watchdog timer
control register is
X
CIN
control register is
written to.
“0”
“10”
written to.
Watchdog timer L (8)
Main clock division
ratio selection bits
(Note)
Watchdog timer H (8)
1/16
“1”
“00”
“01”
Watchdog timer H count
source selection bit
X
IN
STP instruction function selection bit
STP instruction
Reset
circuit
Internal reset
RESET
Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
Fig. 51 Block diagram of Watchdog timer
b0
b7
Watchdog timer control register
(WDTCON : address 003916
)
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction function selection bit
0: Entering Stop mode by execution of STP instruction
1: Internal reset by execution of STP instruction
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/16 or f(XCIN)/16
Fig. 52 Structure of Watchdog timer control register
Rev.1.10 Apr 3, 2006 page 53 of 75
REJ03B0139-0110
RENESAS [ RENESAS TECHNOLOGY CORP ]
