MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Receive
to “0” when reading the low-order byte of the receive buffer register
Receive is enabled when bit 2 (REi flag) of UARTi Transmit/Receive
control register 1 is set to “1.” As shown in Figure 67, the frequency
divider circuit (1/16) at the receiving side begin to work when a start
or when writing “0” to the REi flag or when setting to a parallel port.
The OERi and SUMi flags are cleared to “0” when writing “0” to the
REi flag or when setting to a parallel port.
bit arrives and the data is received.
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The SUMi flag is cleared to “0” when the OERi, FERi, PERi flags are
cleared to “0” all.
If RTSi output is selected by setting bit 2 of UARTi Transmit/Receive
____
control register 0 to “1”, the RTSi output is “H” when the REi flag is
____
“0”. When the REi flag changes to “1”, the RTSi output goes “L” to
indicate receive ready and returns to “H” once receive has started. In
____
Sleep mode
other words, RTSi output can be used to determine externally
whether the receive register is ready to receive.
The sleep mode is used to communicate only between certain micro-
computers when multiple microcomputers are connected through se-
rial I/O.
The entire transmission data bits are received when the start bit
passes the final bit of the receive block shown in Figure 56. At this
point, the contents of the receive register is transferred to the receive
buffer register and bit 3 (Rli flag) of UARTi Transmit/Receive control
The microcomputer enters the sleep mode when bit 7 of UARTi
Transmit/Receive mode register is set to “1.”
The operation of the sleep mode for an 8-bit asynchronous commu-
nication is described below.
register 1 is set to “1.” In other words, the RIi flag indicates that the
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receive buffer register contains data when it is set to “1.” If RTSi out-
____
When sleep mode is selected, the contents of the receive register is
not transferred to the receive buffer register if bit 7 (bit 6 if 7-bit asyn-
chronous communication and bit 8 if 9-bit asynchronous communica-
tion) of the received data is “0”. Also the RIi, OERi, FERi, PERi, and
the SUMi flag are unchanged. Therefore, the interrupt request bit of
the UARTi receive interrupt control register is also unchanged. Nor-
mal receive operation takes place when bit 7 of the received data is
“1”.
put is selected, RTSi output goes “L” to indicate that the register is
ready to receive the next data.
The interrupt request bit of the UARTi receive interrupt control regis-
ter is set to “1” when the RIi flag changes from “0” to “1”.
Bit 4 (OERi flag) of UARTi Transmit/Receive control register 1 is set
to “1” when the next data is transferred from the receive register to
the receive buffer register while the RIi flag is “1”, in other words,
when an overrun error occurs. If the OERi flag is “1”,
it indicates that the next data has been transferred to the receive
buffer register before the contents of the receive buffer register has
been read.
The following is an example of how the sleep mode can be used.
The main microcomputer first sends data: bit 7 is “1” and bits 0 to 6
are set to the address of the subordinate microcomputer to be com-
municated with. Then all subordinate microcomputers receive this
data. Each subordinate microcomputer checks the received data,
clears the sleep bit to “0” if bits 0 to 6 are its own address and sets
the sleep bit to “1” if not. Next, the main microcomputer sends data
with bit 7 cleared. Then the microcomputer which cleared the sleep
bit will receive the data, but the microcomputers which set the sleep
bit to “1” will not. In this way, the main microcomputer is able to com-
municate only with the designated microcomputer.
Bit 5 (FERi flag) is set to “1” when the number of stop bits is less than
required (framing error).
Bit 6 (PERi flag) is set to “1” when a parity error occurs.
Bit 7 (SUMi flag) is set to “1” when either the OERi flag, FERi flag, or
the PERi flag is set to “1.” Therefore, the SUMi flag can be used to
determine whether there is an error.
The setting of the RIi flag, OERi flag, FERi flag, and the PERi flag is
performed while transferring the contents of the receive register to
the receive buffer register. The Rli, FERi, and PERi flags are cleared
Pfi or fEXT
RE
i
Stop bit
Start bit
Start bit
Check to be “L” level
RX
Di
D0
D1
D7
Data fetched
Receive
Clock
Starting at the falling
edge of start bit
RI
i
RTS
i
Fig. 67 Receive timing example when 8-bit asynchronous communication with no parity and 1 stop bit selected
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RENESAS [ RENESAS TECHNOLOGY CORP ]
