MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When the bit of comparator function select register is “0” and bit 3 of
Operation mode
A-D control register 1 is “1”, A-D conversion ends after 59 fAD cycles,
and the interrupt request bit of the A-D interrupt control register is set
to “1.” At the same time, A-D control register 0 bit 6 (A-D conversion
start bit) is cleared to “0” and A-D conversion stops. The result of A-D
conversion is stored in the A-D register corresponding to the selected
pin.
The operation mode is selected by bits 3 and 4 of A-D control regis-
ter 0 and bit 2 of A-D control register 1. The available operation
modes are one-shot, repeat, single sweep, repeat sweep 0, and re-
peat sweep 1. Either an A-D converter or a comparator can be se-
lected respectively for every pin in the following 5 modes. The
following description applies to the case where the bit of the com-
parator function select register is “0” and an A-D converter is se-
lected. It also applies to a comparator’s operation except that an A-D
conversion is changed to a comparator operation and the result of a
comparison is stored into the comparator result register.
When the bit of the comparator function select register is “1”, a com-
parator operation ends after 14 fAD cycles and the interrupt request
bit of the A-D interrupt control register is set to “1”. At the same
time, the A-D control register 0 bit 6 (A-D conversion start bit) is
cleared to “0” and the comparator operation stops. The result of the
comparison is stored into the bit of the comparator result register cor-
responding to the selected pin.
(1) One-shot mode
One-shot mode is selected when bits 3 and 4 of A-D control register
0 are “0” and bit 2 of A-D control register 1 is “0”. The A-D conversion
pins are selected with bits 0 to 2 of A-D control register 0. A-D con-
version can be started by a software trigger or by an external trigger.
A software trigger is selected when bit 5 of A-D control register 0 is
“0” and an external trigger is selected when it is “1”. When a software
trigger is selected, A-D conversion or comparator operation is started
when bit 6 (A-D conversion start flag) is set to “1.”
If an external trigger is selected, A-D conversion starts when the A-D
_____
conversion start bit is “1” and the ADTRG input changes from “H” to
“L”. In this case, the pins that can be used for A-D conversion are AN0
_____
to AN6 because the ADTRG pin is multiplexed with analog voltage in-
put pin AN7. This operation is the same as that for software trigger
except that the A-D conversion start bit is not cleared after A-D con-
version and a retrigger can be available during A-D conversion.
Address
7
×
6
×
5
4
3
2
1
0
Address
1F16
A-D control register 1
7
6
5
4
3
2
1
0
1E16
A-D control register 0
Analog input select bit
A-D sweep pin select bit
When single sweep or repeat sweep
mode 0 is selected
0 0 0 : Select AN
0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
, AN1
(2 pins)
(4 pins)
(6 pins)
(8 pins)
0 0 1 : Select AN
0 1 0 : Select AN
0 1 1 : Select AN
1 0 0 : Select AN
1 0 1 : Select AN
1
2
3
4
5
– AN
– AN
– AN
3
5
7
When repeat sweep mode 1 is selected
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
(1 pins)
(2 pins)
(3 pins)
(4 pins)
1 1 0 : Select AN
6
, AN
– AN
– AN
1
1 1 1 : Select AN
7
2
3
A-D operation mode select bit 0
0 0 : One-shot mode
A-D operation mode select bit 1
0 : Other than repeat sweep mode 1
1 : Repeat sweep mode 1
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0
Repeat sweep mode 1
Trigger select bit
0 : Software trigger
A-D converter frequency select bit 1
1 : ADTRG input trigger
A-D conversion start bit
0 : Stop A-D conversion
1 : Start A-D conversion
A-D conversion frequency select bit 0
V
REF connection select bit (Note 5)
0 : VREF is connected
1 : VREF is not connected
These bits are not used for A-D converter.
A-D conversion frequency select bit
A-D conversion frequency select bit
Bit 6 at address
5F16 (Note 1)
Bit 2 at address
5F16 (Note 2)
Bit 6 at address
5F16 (Note 1)
Bit 2 at address
5F16 (Note 2)
fAD
fAD
Bit 1
0
Bit 0
0
Bit 1
0
Bit 0
0
f(XIN)/8
f(XIN)/4
f(XIN)/2
f(XIN) (Note 4)
f(XIN)/4
f(XIN)/2
f(XIN)/16
f(XIN)/8
0
1
0
1
0
1
0
1
1
0
1
0
f(XIN)/4
1
1
1
1
f(XIN)/2 (Note 3)
f(XIN)/8
0
1
0
0
0
0
0
1
0
1
f(XIN)/4
1
0
1
0
f(XIN)
f(XIN)/2
1
1
1
1
Notes1, 2: Refer to Figure 9 Processor mode register 1 bit configuration.
3: When f(XIN) > 25 MHz, this can be selected only in 8-bit resolution
mode.
Notes 4: When f(XIN) > 12.5 MHz, this can be selected only in 8-bit resolution mode.
5: When the expansion function select bit (bit 5 of particular function select
register 1 ; refer to Fig. 62) is “1”, bit 5 can be written and changed.
Fig. 71 A-D control register bit configuration
58
RENESAS [ RENESAS TECHNOLOGY CORP ]
