MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pulse mode 0
7
6
5
4
3
2
1
0
Address
This mode divides a pulse output port into 4 bits and 4 bits and indi-
Waveform output mode register 1A16
vidually controls them.
Waveform output select bits
000 : Parallel port
When setting the pulse output mode select bit to “0”, and setting bits
2 and 1 to “0” and bit 0 to “1” of the waveform output select bits, four
of RTP13, RTP12, RTP11, and RTP10 become the pulse output
ports with RTP1 selected.
001 : RTP1 selected
(Valid in pulse mode 0)
010 : RTP0 selected
(Valid in pulse mode 0)
011 : In pulse mode 0
RTP1 and RTP0 selected
In pulse mode 1
When setting the pulse output mode select bit to “0”, and setting bits
2 and 0 to “0” and bit 1 to “1” of the waveform output select bits, four
of RTP03, RTP02, RTP01, RTP00 become the pulse output ports
with RTP0 selected.
RTP1, RTP0
3
, RTP0
2,
RTP0 , RTP0
1
0 selected
When setting the pulse output mode select bit to “0”, and setting bit
2 to “0” and bits 1 and 0 to “1” of the waveform output select bits,
the following two groups become the pulse output ports with RTP1
and RTP0 selected:
Polarity select bit
(Valid for RTP0 in pulse mode 0)
0 : Positive polarity
1 : Negative polarity
•Four of RTP13, RTP12, RTP11, RTP10
Pulse width modulation select bit 0
(Valid for RTP1 in pulse mode 0;
•Four of RTP03, RTP02, RTP01, RTP00.
Valid for RTP1, RTP0
pulse mode 1)
3, RTP02 in
Each time the contents of timer A1 counter become 000016, the
contents of pulse output data register 1 (low-order 4 bits at address
1C16) corresponding to RTP13, RTP12, RTP11, RTP10 are output
from ports.
0 : No modulation by timer A2
1 : Modulation by timer A2
Pulse width modulation select bit 1*
(Valid in pulse mode 1)
0 : Modulation by timer A2
Each time the contents of timer A0 counter become 000016, the
contents of pulse output data register 0 (low-order 4 bits at address
1D16) corresponding to RTP03, RTP02, RTP01, RTP00 are output
from ports.
1 : Modulation for RTP0
by timer A2
3, RTP02
Modulation for RTP1
by timer A3
Modulation for RTP1
by timer A4
1
3
, RTP1
, RTP1
0
2
When writing “0” to the specified bit of pulse output data register, “L”
level is output from the pulse output port when the contents of cor-
responding timer counter become 000016; when writing “1” to it, “H”
level is output from the pulse output port.
* when selecting pulse mode 0, fix
this bit to “0”.
Waveform output control bit 0
0 : In pulse mode 0
Disable RTP0 waveform output
In pulse mode 1
Disable RTP0
output
1 : In pulse mode 0
Enable RTP0 waveform output
In pulse mode 1
1, RTP00 waveform
Address
Timer A0 mode register 5616
Timer A1 mode register 5716
7
6
5
0
4
0
3
×
2
1
1
0
0
0
100 : Fix to “100” in pulse output port mode
Enable RTP0
output
1, RTP00 waveform
×
: Not used in pulse output port mode
Waveform output control bit 1
0 : In pulse mode 0
00 : Fix to “00” in pulse output port mode
Clock source select bit
00 : Pf2 selected
01 : Pf16 selected
10 : Pf64 selected
11 : Pf512 selected
Disable RTP1 waveform output
In pulse mode 1
Disable RTP1, RTP0
waveform output
3, RTP02
1 : In pulse mode 0
Enable RTP1 waveform output
In pulse mode 1
Fig. 50 Bit configuration of timer A1 and A0 mode registers in pulse
output port mode
Enable RTP1, RTP0
waveform output
3, RTP02
Note : Only when bit 5 of the particular function select register 1
(in Fig. 15) is set to “1”, this register’s contents can be
changed from the status after reset (in Fig.76).
Fig. 49 Bit configuration of waveform output mode register in pulse
output port mode
43
RENESAS [ RENESAS TECHNOLOGY CORP ]
