M37161M8/MA/MF-XXXSP/FP,M37161EFSP/FP
The horizontal display start position is common to all blocks, and can
be set in 128 steps (where 1 step is 4TOSC, TOSC being the OSD
oscillation cycle) as values “0016” to “FF16” in bits 0 to 6 of the hori-
zontal position register (address 00D116). The horizontal position reg-
ister is shown in Figure 8.10.9.
Horizontal Position Register
b7 b6 b5b4 b3 b2b1 b0
Horizontal position register (HP) [Address 00D116
]
B
0
Name
Functions
After reset R W
Horizontal display start position
4Tosc ✕ n
Horizontal display start
0
R W
to position control bits
6
(n: setting value, Tosc: OSD oscillation cycle)
(HP0 to HP6)
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
7
0
R —
Note: The setting value synchronizes with the V SYNC
.
Fig. 8.10.9 Horizontal Position Register
Notes 1 : 1TC (TC : OSD clock cycle divided in pre-divide circuit) gap occurs
between the horizontal display start position set by the horizontal
position register and the most left dot of the 1st block. Accordingly,
when 2 blocks have different pre-divide ratios, their horizontal dis-
play start position will not match.
2 : When setting “0016” to the horizontal position register, it needs an
approximately 62TOSC (= Tdef) interval from a rising edge (when nega-
tive polarity is selected) of HSYNC signal to the horizontal display start
position.
H
SYNC
1T
C
T
def
4TOSC 5 N
Note 1
Block 2 (Pre-divide ratio = 2)
Block 3 (Pre-divide ratio = 3)
1TC
N
1T
: Value of horizontal position register (decimal notation)
: OSD clock cycle divided in pre-divide circuit
C
T
T
OSC : OSD oscillation cycle
def : 62 TOSC
Fig. 8.10.10 Notes on Horizontal Display Start Position
Rev.1.00 2003.11.25 page 58 of 128
RENESAS [ RENESAS TECHNOLOGY CORP ]
