M37161M8/MA/MF-XXXSP/FP,M37161EFSP/FP
(4) Serial I/O interrupt
This is an interrupt request from the clock synchronous serial I/O
function.
Interrupt request bit
Interrupt enable bit
(5) f(XIN)/4096 interrupt
The f (XIN)/4096 interrupt occurs regularly with a f(XIN)/4096 pe-
riod. Set bit 0 of the PWM mode register 1 to “0.”
Interrupt disable flag I
2
(6) Multi-master I C-BUS interface interrupt
2
This is an interrupt request related to the multi-master I C-BUS
Interrupt
request
BRK instruction
Reset
interface.
(7) Timer 5 • 6 interrupt
An interrupt is generated by an overflow of timer 5 or 6. Their
priorities are same, and can be switched by software.
Fig. 8.3.1 Interrupt Control
(8) BRK instruction interrupt
This software interrupt has the least significant priority. It does
not have a corresponding interrupt enable bit, and it is not af-
fected by the interrupt disable flag I (non-maskable).
Rev.1.00 2003.11.25 page 18 of 128
RENESAS [ RENESAS TECHNOLOGY CORP ]
