M37161M8/MA/MF-XXXSP/FP,M37161EFSP/FP
ꢀ SFR1 Area (addresses E016 to FF16
)
<Bit allocation>
:
<State immediately after reset>
: “0” immediately after reset
: “1” immediately after reset
0
1
?
Function bit
Name
:
: No function bit
: Indeterminate immediately
after reset
0
1
: Fix this bit to “0”
(do not write “1”)
: Fix this bit to “1”
(do not write “0”)
Bit allocation
State immediately after reset
Address
Register
b7
b0 b7
b0
?
?
?
E016
E116
E216
E316
?
?
?
?
E416
E516
E616
?
?
?
E716
E816
E916
?
0016
Serial I/O register (SIO)
EA16
EB16
SM6 SM5
SM3 SM2 SM1 SM0
Serial I/O mode register (SM)
0
0
ADC14
ADC12 ADC11 ADC10
0
0
0
?
0
EC16 A-D control register 1 (AD1)
0
0
0
ADC26 ADC25 ADC24 ADC23 ADC22 ADC21 ADC20
0016
0716
A-D control register 2 (AD2)
Timer 5 (T5)
ED16
EE16
EF16
F016
Timer 6 (T6)
FF16
FF16
0716
FF16
0716
Timer 1 (T1)
Timer 2 (T2)
F116
F216
F316
Timer 3 (T3)
Timer 4 (T4)
TM17 TM16 TM15 TM14 TM13 TM12 TM11 TM10
TM27 TM26 TM25 TM24 TM23 TM22 TM21 TM20
0016
F416 Timer mode register 1 (TM1)
Timer mode register 2 (TM2)
2
F516
0016
?
D7 D6 D5 D4 D3 D2 D1 D0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
F616 I C data shift register (S0)
2
0016
F716
F816
I C address register (S0D)
2
MST TRX BB PIN AL AAS AD0 LRB
10BIT
0
0
0
1
0
0
0
?
I C status register (S1)
BSEL1 BSEL0
ALS ESO BC2 BC1 BC0
CCR4 CCR3 CCR2 CCR1 CCR0
2
0016
SAD
FAST
MODE
I C control register (S1D)
F916
FA16
FB16
FC16
FD16
FE16
FF16
ACK
ACK
2
0016
3C16
0016
0016
0016
0016
BIT
I C clock control register (S2)
CM2
CM7 CM6 CM5
0
1
1
0
CPU mode register (CPUM)
VSCR OSDR TM4R TM3R TM2R TM1R
IN3R
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
TM56R
CK0
0
IN1R
IICR IN2R CKR S1R
0
VSCE OSDE TM4E TM3E TM2E TM1E
IN3E
TM56C TM56E
IICE IN2E CKE S1E
0
IN1E
Fig. 8.2.3 Memory Map of Special Function Register 1 (SFR1) (2)
Rev.1.00 2003.11.25 page 14 of 128