M37161M8/MA/MF-XXXSP/FP,M37161EFSP/FP
ꢀSFR2 Area (addresses 20016 to 20F16)
<Bit allocation>
<State immediately after reset>
:
:
0
1
?
: “0” immediately after reset
: “1” immediately after reset
Function bit
Name
: No function bit
: Indeterminate immediately
after reset
0
1
: Fix this bit to “0”
(do not write “1”)
: Fix this bit to “1”
(do not write “0”)
State immediately after reset
Register
Bit allocation
Address
b0
b0
b7
b7
?
?
?
?
?
?
?
20016
20116
20216
20316
PWM0 register (PWM0)
PWM1 register (PWM1)
PWM2 register (PWM2)
PWM3 register (PWM3)
20416 PWM4 register (PWM4)
20516
20616
0016
DA-H register (DAH)
20716
20816
20916
0
?
0
?
?
?
?
0
?
0
?
?
?
?
?
0
DA-L register (DAL)
PWM mode register 1 (PM1)
PM14 PM13
PM10
PM25 PM24 PM23 PM22 PM21 PM20
PWM mode register 2 (PM2)
0
0
0016
0016
0016
0016
0016
0016
?
20A16
20B16
20C16
ROM correction address 1 (high-order)
ROM correction address 1 (low-order)
ROM correction address 2 (high-order)
20D16
20E16
ROM correction address 2 (low-order)
ROM correction enable register (RCR)
RC1 RC0
20F16
21016
21116
0
0
0
0
1
1
1
0
Clock frequency set register (CFS)
Clock control register 2(CC2)
0016
0016
0016
0
1
0
0
0
0
0
0
1
0
0
0
0
0
CC37
CC35
21216 Clock control register 3(CC3)
21316
0
0
0
0
0
0
0
0
Test register
Fig. 8.2.4 Memory Map of Special Function Register 2 (SFR2)
Rev.1.00 2003.11.25 page 15 of 128
RENESAS [ RENESAS TECHNOLOGY CORP ]
