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M37161EFSP 参数 Datasheet PDF下载

M37161EFSP图片预览
型号: M37161EFSP
PDF下载: 下载PDF文件 查看货源
内容描述: 单片8位CMOS微机 [SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER]
分类和应用: 微控制器和处理器外围集成电路光电二极管计算机可编程只读存储器时钟
文件页数/大小: 129 页 / 1075 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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M37161M8/MA/MF-XXXSP/FP,M37161EFSP/FP  
Interrupt Control Register 1  
b7b6 b5b4b3 b2b1b0  
Interrupt control register 1 (ICON1) [Address 00FE16]  
Name  
After reset  
0
B
0
Functions  
R W  
R W  
Timer 1 interrupt  
enable bit (TM1E)  
0 : Interrupt disabled  
1 : Interrupt enabled  
0 : Interrupt disabled  
1 : Interrupt enabled  
0 : Interrupt disabled  
1 : Interrupt enabled  
1
2
3
4
Timer 2 interrupt  
enable bit (TM2E)  
Timer 3 interrupt  
enable bit (TM3E)  
Timer 4 interrupt  
enable bit (TM4E)  
R W  
R W  
R W  
R W  
0
0
0
0
0 : Interrupt disabled  
1 : Interrupt enabled  
0 : Interrupt disabled  
1 : Interrupt enabled  
OSD interrupt enable bit  
(OSDE)  
VSYNC interrupt enable 0 : Interrupt disabled  
5
6
7
R W  
R W  
R —  
0
0
1 : Interrupt enabled  
bit (VSCE)  
0 : Interrupt disabled  
1 : Interrupt enabled  
INT3 external interrupt  
enable bit (IN3E)  
Nothing is assigned. This bit is a write disable  
bit. When this bit is read out, the value is 0.”  
0
Fig. 8.3.4 Interrupt Control Register 1  
Interrupt Control Register 2  
b7b6 b5b4b3 b2b1b0  
0
Interrupt control register 2 (ICON2) [Address 00FF16  
]
After reset  
0
B
0
Name  
Functions  
R W  
R W  
INT1 external interrupt  
enable bit (IN1E)  
0 : Interrupt disabled  
1 : Interrupt enabled  
1
2
3
4
0
R W  
Fix this bit to 0.”  
Serial I/O interrupt  
enable bit (SIE)  
0 : Interrupt disabled  
1 : Interrupt enabled  
0
0
0
R W  
R W  
R W  
0 : Interrupt disabled  
1 : Interrupt enabled  
0 : Interrupt disabled  
1 : Interrupt enabled  
f(XIN  
)/4096 interrupt  
enable bit (CKE)  
INT2 external interrupt  
enable bit (IN2E)  
I2  
Multi-master C-BUS  
5
0 : Interrupt disabled  
1 : Interrupt enabled  
0
R W  
interface interrupt enable  
bit (IICE)  
0
0
R W  
R W  
Timer 5 6 interrupt  
enable bit (TM56E  
Timer 5 6 interrupt  
switch bit (TM56C)  
0 : Interrupt disabled  
1 : Interrupt enabled  
6
7
)
0 : Timer 5  
1 : Timer 6  
Fig. 8.3.5 Interrupt Control Register 2  
Rev.1.00 2003.11.25 page 20 of 128  
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