M37161M8/MA/MF-XXXSP/FP,M37161EFSP/FP
Address 00FB16
CPU Mode Register
b7b6 b5b4b3 b2b1b0
1
1
0 0
CPU mode register (CM) [Address 00FB16
]
Functions
After reset
0
B
Name
R W
R W
b1 b0
Processor mode bits
(CM0, CM1)
0, 1
0 0: Single-chip mode
0 1:
1 0:
1 1:
Not available
0: 0 page
1: 1 page
Stack page selection
bit (CM2) (See note1)
2
1
R W
Fix these bits to “1.”
1
1
R W
R W
3, 4
5
0: LOW drive
1: HIGH drive
X
COUT drivability
selection bit (CM5)
6
7
0
0
R W
R W
0: Oscillating
1: Stopped
Main Clock (XIN-XOUT
)
stop bit
(CM6)
Internal system clock 0:
selection bit
X
IN-XOUT selected
(high-speed mode)
1: XCIN–XCOUT selected
(low-speed mode)
(CM7)
Note 1: This bit is set to “1” after the reset release.
Address 00FC16
Interrupt Request Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address 00FC16
]
B
0
Name
Functions
Afrer reset R W
0
0 : No interrupt request issued
1 : Interrupt request issued
Timer 1 interrupt request
bit (TM1R)
✕
✕
R
1
2
3
4
5
6
7
Timer 2 interrupt request 0 : No interrupt request issued
bit (TM2R) 1 : Interrupt request issued
0
0
0
R
Timer 3 interrupt request 0 : No interrupt request issued
bit (TM3R) 1 : Interrupt request issued
✕
✕
✕
R
R
R
Timer 4 interrupt request 0 : No interrupt request issued
bit (TM4R)
1 : Interrupt request issued
OSD interrupt
request bit (OSDR)
0 : No interrupt request issued
1 : Interrupt request issued
0
0
0
0
VSYNC interrupt request 0 : No interrupt request issued
bit (VSCR)
✕
✕
—
R
R
R
1 : Interrupt request issued
INT3 external interrupt
request bit (IN3R)
0 : No interrupt request issued
1 : Interrupt request issued
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
✕: “0” can be set by software, but “1” cannot be set.
Rev.1.00 2003.11.25 page 120 of 128
RENESAS [ RENESAS TECHNOLOGY CORP ]
