M37161M8/MA/MF-XXXSP/FP,M37161EFSP/FP
Address 00F516
Timer Mode Register 2
b7b6 b5b4b3 b2b1b0
Timer mode register 2 (TM2) [Address 00F516
]
After reset
0
B
0
Name
Functions
R W
R W
Timer 3 count source
selection bit (TM20)
(b6 at address 00C716
)
b0
0
1
0
1
0 : f(XIN)/16 or f(XCIN)/16 (See note)
0 : f(XCIN
)
1 :
1 :
External clock from TIM3 pin
b4 b1
1, 4
Timer 4 count source
selection bits
(TM21, TM24)
0
R W
0
0
1
1
0 : Timer 3 overflow signal
1 : f(XIN)/16 or f(XCIN)/16 (See note)
0 : f(XIN)/2 or f(XCIN)/2 (See note)
1 : f(XCIN
)
Timer 3 count
stop bit (TM22)
2
3
0: Count start
1: Count stop
0
0
R W
R W
Timer 4 count stop bit
(TM23)
0: Count start
1: Count stop
Timer 5 count stop bit
(TM25)
5
6
0: Count start
1: Count stop
0
0
R W
R W
Timer 6 count stop bit
(TM26)
0: Count start
1: Count stop
Timer 5 count source
selection bit 1
(TM27)
7
0: f(XIN)/16 or f(XCIN)/16 (See note)
1: Count source selected by bit 6
of TM1
0
R W
Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Address 00F616
2
I C Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0
2
I C data shift register 1(S0) [Address 00F616]
B
Name
Functions
After reset
R
R
W
W
0
to
7
D0 to D7 This is an 8-bit shift register to store
receive data and write transmit data.
Indeterminate
2
Note : To write data into the I C data shift register after setting the MST bit to
“0” (slave mode), keep an interval of 8 machine cycles or more.
Rev.1.00 2003.11.25 page 116 of 128
RENESAS [ RENESAS TECHNOLOGY CORP ]
