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M32180F8TFP 参数 Datasheet PDF下载

M32180F8TFP图片预览
型号: M32180F8TFP
PDF下载: 下载PDF文件 查看货源
内容描述: 32位RISC单芯片微型计算机M32R系列M32R / ECU系列 [32-Bit RISC Single-Chip Microcomputers M32R Family M32R/ECU Series]
分类和应用: 计算机
文件页数/大小: 839 页 / 3694 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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DMAC  
9.2 DMAC Related Registers  
9
9.2.3 DMA Source Address Registers  
DMA0 Source Address Register (DM0SA)  
DMA1 Source Address Register (DM1SA)  
DMA2 Source Address Register (DM2SA)  
DMA3 Source Address Register (DM3SA)  
DMA4 Source Address Register (DM4SA)  
DMA5 Source Address Register (DM5SA)  
DMA6 Source Address Register (DM6SA)  
DMA7 Source Address Register (DM7SA)  
DMA8 Source Address Register (DM8SA)  
DMA9 Source Address Register (DM9SA)  
<Address: H’0080 0412>  
<Address: H’0080 0422>  
<Address: H’0080 0432>  
<Address: H’0080 0442>  
<Address: H’0080 0452>  
<Address: H’0080 041A>  
<Address: H’0080 042A>  
<Address: H’0080 043A>  
<Address: H’0080 044A>  
<Address: H’0080 045A>  
b0  
?
1
?
2
?
3
?
4
?
5
?
6
?
7
8
9
?
10  
?
11  
?
12  
?
13  
?
14  
?
b15  
?
DM0SA–DM9SA  
?
?
<After reset: Undefined>  
b
Bit Name  
Function  
R
R
W
W
0–15  
DM0SA–DMA9SA  
Source address bits A16–A31  
(A0–A15 are fixed to H’0080)  
Note: • This register must always be accessed in halfwords.  
The DMA Source Address Register is used to set the source address of DMA transfer in such a way that bit 0  
and bit 5 correspond to A16 and A31, respectively. Because this register is comprised of a current register, the  
values read from this register are always the current value.  
When DMA transfer finishes (i.e., the Transfer Count Register underflows), the value in this register if “Address  
fixed” is selected, is the same source address that was set in it before the DMA transfer began; if “Address  
incremental” is selected, the value in this register is the last transfer address + 1 (for 8-bit transfer) or the last  
transfer address + 2 (for 16-bit transfer).  
The DMA Source Address Register must always be accessed in halfwords (16 bits) beginning with an even  
address. If accessed in bytes, the value in this register is undefined.  
(1) DM0SA–DM9SA (Source Address bits A16–A31)  
Set this register to specify the source address of DMA transfer in the internal I/O or RAM space from the  
address H’0080 0000 to the address H’0080 FFFF.  
The 16 high-order source address bits (A0–A15) are always fixed to H’0080. Use this register to set the 16  
low-order source address bits (with bit 0 corresponding to the source address A16, and bit 15 corresponding  
to the source address A31).  
32180 Group User’s Manual (Rev.1.0)  
9-19  
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