DMAC
9.2 DMAC Related Registers
9
9.2.5 DMA Transfer Count Registers
DMA0 Transfer Count Register (DM0TCT)
DMA1 Transfer Count Register (DM1TCT)
DMA2 Transfer Count Register (DM2TCT)
DMA3 Transfer Count Register (DM3TCT)
DMA4 Transfer Count Register (DM4TCT)
DMA5 Transfer Count Register (DM5TCT)
DMA6 Transfer Count Register (DM6TCT)
DMA7 Transfer Count Register (DM7TCT)
DMA8 Transfer Count Register (DM8TCT)
DMA9 Transfer Count Register (DM9TCT)
<Address: H’0080 0416>
<Address: H’0080 0426>
<Address: H’0080 0436>
<Address: H’0080 0446>
<Address: H’0080 0456>
<Address: H’0080 041E>
<Address: H’0080 042E>
<Address: H’0080 043E>
<Address: H’0080 044E>
<Address: H’0080 045E>
b0
?
1
?
2
?
3
?
4
?
5
?
6
?
7
8
9
?
10
?
11
?
12
?
13
?
14
?
b15
?
DM0TCT–DM15TCT
?
?
<After reset: Undefined>
b
Bit Name
Function
R
R
W
W
0–15
DM0TCT–DM9TCT
(Has no effect during ring buffer mode)
Note: • This register must always be accessed in halfwords.
DMA transfer count
The DMA Transfer Count Register is used to set the number of times data is transferred on each channel.
However, the value in this register has no effect during ring buffer mode.
The transfer count is the (value set in the transfer count register + 1). Because the DMA Transfer Count Register
is comprised of a current register, the values read from this register are always the current value. (However, if
the register is read in a cycle immediately after transfer, the value obtained is one that was stored in the count
register before the transfer began.) When transfer finishes, this count register underflows and the value read
from it is H’FFFF.
When transfer is enabled, this register is protected in hardware and cannot be accessed for write.
During ring buffer mode, the transfer count register counts down in free-run mode and continues counting until
transfer is disabled. No interrupt is generated at underflow.
If any cascaded channel exists, each time one DMA transfer (byte or halfword) is completed or when all trans-
fers on a channel are completed (i.e., the transfer count register underflows), transfer on the cascaded channel
starts.
The DMA Transfer Count Register must always be accessed in halfwords (16 bits) beginning with an even
address. If accessed in bytes, the value in this register is undefined.
32180 Group User’s Manual (Rev.1.0)
9-21
RENESAS [ RENESAS TECHNOLOGY CORP ]
