DMAC
9.2 DMAC Related Registers
9
9.2.4 DMA Destination Address Registers
DMA0 Destination Address Register (DM0DA)
DMA1 Destination Address Register (DM1DA)
DMA2 Destination Address Register (DM2DA)
DMA3 Destination Address Register (DM3DA)
DMA4 Destination Address Register (DM4DA)
DMA5 Destination Address Register (DM5DA)
DMA6 Destination Address Register (DM6DA)
DMA7 Destination Address Register (DM7DA)
DMA8 Destination Address Register (DM8DA)
DMA9 Destination Address Register (DM9DA)
<Address: H’0080 0414>
<Address: H’0080 0424>
<Address: H’0080 0434>
<Address: H’0080 0444>
<Address: H’0080 0454>
<Address: H’0080 041C>
<Address: H’0080 042C>
<Address: H’0080 043C>
<Address: H’0080 044C>
<Address: H’0080 045C>
b0
?
1
?
2
?
3
?
4
?
5
?
6
?
7
8
9
?
10
?
11
?
12
?
13
?
14
?
b15
?
DM0DA–DM9DA
?
?
<After reset: Undefined>
b
Bit Name
Function
R
R
W
W
0–15
DM0DA–DM9DA
Destination address bits A16–A31
(A0–A15 are fixed to H’0080)
Note: • This register must always be accessed in halfwords
The DMA Destination Address Register is used to set the destination address of DMA transfer in such a way that
bit 0 and bit 15 correspond to A16 and A31, respectively. Because this register is comprised of a current register,
the values read from this register are always the current value.
When DMA transfer finishes (i.e., the Transfer Count Register underflows), the value in this register if “Address
fixed” is selected, is the same source address that was set in it before the DMA transfer began; if “Address
incremental” is selected, the value in this register is the last transfer address + 1 (for 8-bit transfer) or the last
transfer address + 2 (for 16-bit transfer).
The DMA Destination Address Register must always be accessed in halfwords (16 bits) beginning with an even
address. If accessed in bytes, the value in this register is undefined.
(1) DM0DA–DM9DA (Destination Address bits A16–A31)
Set this register to specify the destination address of DMA transfer in the internal I/O or RAM space from the
address H’0080 0000 to the address H’0080 FFFF.
The 16 high-order destination address bits (A0–A15) are always fixed to H’0080. Use this register to set the
16 low-order destination address bits (with bit 0 corresponding to the destination address A16, and bit 15
corresponding to the destination address A31).
32180 Group User’s Manual (Rev.1.0)
9-20
RENESAS [ RENESAS TECHNOLOGY CORP ]
