M32C/83 Group (M32C/83, M32C/83T)
VCC=3.3V
o
Timing Requirements (VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85 C unless otherwise specified)
Table 5.28 External Clock Input
Standard
Symbol
Parameter
Unit
Min
50
Max
tc
External Clock Input Cycle Time
ns
ns
ns
ns
ns
tw(H)
tw(L)
tr
External Clock Input High ("H") Pulse Width
External Clock Input Low ("L") Pulse Width
External Clock Rise Time
22
22
5
5
tf
External Clock Fall Time
Table 5.29 Memory Expansion Mode and Microprocessor Mode
Standard
Symbol
Parameter
Unit
Min
Max
tac1(RD-DB)
tac1(AD-DB)
tac2(RD-DB)
tac2(AD-DB)
tac3(RD-DB)
tac3(AD-DB)
Data Input Access Time (RD standard, with no wait state)
(Note 1) ns
(Note 1) ns
(Note 1) ns
(Note 1) ns
(Note 1) ns
(Note 1) ns
(Note 1) ns
(Note 1) ns
(Note 1) ns
ns
Data Input Access Time (AD standard, CS standard, with no wait state)
Data Input Access Time (RD standard, with a wait state)
Data Input Access Time (AD standard, CS standard, with a wait state)
Data Input Access Time (RD standard, when accessing a space with the multiplexed bus)
Data Input Access Time (AD standard, CS standard, when accessing a space with the multiplexed bus)
tac4(RAS-DB) Data Input Access Time (RAS standard, when accessing a DRAM space)
tac4(CAS-DB) Data Input Access Time (CAS standard, when accessing a DRAM space)
tac4(CAD-DB) Data Input Access Time (CAD standard, when accessing a DRAM space)
tsu(DB-BCLK)
Data Input Setup Time
30
40
60
0
tsu(RDY-BCLK) RDY Input Setup Time
tsu(HOLD-BCLK) HOLD Input Setup Time
ns
ns
th(RD-DB)
Data Input Hold Time
Data Input Hold Time
RDY Input Hold Time
ns
th(CAS-DB)
th(BCLK-RDY)
0
ns
0
ns
th(BCLK-HOLD) HOLD Input Hold Time
td(BCLK-HLDA) HLDA Output Delay Time
NOTES:
0
ns
25
ns
1. Values can be obtained from the following equations, according to BCLK frequency. Insert a wait state or lower
operation frequency, f(BCLK), if the calculated value is negative.
109
– 35
– 35
t
ac1(RD – DB)
=
=
[ns]
[ns]
f
(BCLK) X 2
10 9
(BCLK)
t
ac1(AD – DB)
f
109X m
(BCLK) X 2
109 X n
[ns] (m=3 with 1 wait state, m=5 with 2 wait states
and m=7 with 3 wait states)
– 35
– 35
– 35
– 35
t
ac2(RD – DB)
=
=
=
=
f
t
ac2(AD – DB)
[ns] (n=2 with 1 wait state, n=3 with 2 wait states
and n=4 with 3 wait states)
f(BCLK)
109 X m
(BCLK) X 2
[ns] (m=3 with 2 wait states and m=5 with 3 wait states)
[ns] (n=5 with 2 wait states and n=7 with 3 wait states)
[ns] (m=3 with 1 wait state and m=5 with 2 wait states)
t
ac3(RD – DB)
f
109 X n
(BCLK) X 2
t
ac3(AD – DB)
f
109X m
– 35
t
ac4(RAS – DB)
ac4(CAS – DB)
=
=
=
f(BCLK) X 2
109 X n
– 35
– 35
[ns] (n=1 with 1 wait state and n=3 when 2 wait states)
[ns] (l=1 with 1 wait state and l=2 with 2 wait states)
t
f
(BCLK) X 2
109X l
t
ac4(CAD – DB)
f
(BCLK)
Page 66
Rev. 1.41 Jan.31, 2006
REJ03B0013-0141
of 91
RENESAS [ RENESAS TECHNOLOGY CORP ]
