M32C/83 Group (M32C/83, M32C/83T)
VCC=5V
Switching Characteristics
o
(VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85 C unless otherwise specified)
Table 5.20 Memory Expansion Mode and Microprocessor Mode (with No Wait State)
Standard
Measurement
Symbol
Parameter
Address Output Delay Time
Unit
Condition
Min
Max
18
td(BCLK-AD)
th(BCLK-AD)
ns
ns
Address Output Hold Time (BCLK standard)
-3
0
th(RD-AD)
Address Output Hold Time (RD standard)
Address Output Hold Time (WR standard)
Chip-select Signal Output Delay Time
Chip-select Signal Output Hold Time (BCLK standard)
Chip-select Signal Output Hold Time (RD standard)
Chip-select Signal Output Hold Time (WR standard)
ALE Signal Output Delay Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
th(WR-AD)
(Note 1)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
18
-3
0
See Figure 5.1
th(WR-CS)
(Note 1)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
18
18
18
ALE Signal Output Hold Time
-2
-5
RD Signal Output Delay Time
RD Signal Output Hold Time
WR Signal Output Delay Time
th(BCLK-WR) WR Signal Output Hold Time
-3
td(DB-WR)
th(WR-DB)
tw(WR)
Data Output Delay Time (WR standard)
(Note 1)
(Note 1)
(Note 1)
Data Output Hold Time (WR standard)
WR Output Width
NOTES:
1. Values can be obtained from the following equations, according to BCLK frequency.
10 9
td(DB – WR)
th(WR – DB)
th(WR – AD)
th(WR – CS)
=
=
=
=
– 20
[ns]
f
(BCLK)
10 9
[ns]
[ns]
[ns]
– 10
f
(BCLK) X 2
10 9
– 10
– 10
f
(BCLK) X 2
10 9
f
(BCLK) X 2
10 9
tw(WR)
=
[ns]
– 15
f
(BCLK) X 2
Page 51
Rev. 1.41 Jan.31, 2006
REJ03B0013-0141
of 91
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